Senior ASIC Design Verification Engineer, Cloud

Google•Sunnyvale, CA
•$163,000 - $236,000

About The Position

As an ASIC Design Verification Engineer, you will help develop ASICs that accelerate computation in data centers, with a focus on Google TPU architecture and integration within AI/ML-driven systems. You will verify complex digital designs and contribute to project definition, design verification, and silicon bring-up. The role also involves participating in the architecture, documentation, and verification of next-generation data center accelerators. You will work with a team developing custom silicon solutions for AI/ML hardware acceleration and Google’s TPU technology. The AI and Infrastructure team delivers AI and infrastructure capabilities at scale, efficiency, reliability, and velocity for Google customers, Googlers, and users worldwide.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience with design verification.
  • Experience verifying digital logic at RTL using SystemVerilog/UVM for ASICs.

Nice To Haves

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
  • 10 years of experience with industry-standard tools, languages, and methodologies relevant to developing silicon-based ICs and chips.
  • Experience with the full verification life cycle.
  • Experience with three or more SoC projects or cycles and verifying interconnect IPs.

Responsibilities

  • Plan verification of complex digital design blocks by understanding design specifications and working with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM.
  • Identify and write coverage measures for stimulus and corner cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and demonstrate progress toward tape-out.
  • Contribute to project definition, design verification, and silicon bring-up.
  • Participate in the architecture, documentation, and verification of next-generation data center accelerators.

Benefits

  • 15% bonus target
  • Equity
  • Benefits
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service