Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)

Teradyne•Agoura Hills, CA

1d•$192,300 - $307,600•Onsite

About The Position

Teradyne's Silicon Technology Engineering team is seeking an experienced Senior ASIC Chip Lead / Project Lead to drive the development and delivery of a large-scale mixed-signal ASIC for next-generation Automated Test Equipment (ATE) systems. This role requires a proven leader who can drive complex ASIC programs from concept through production, coordinating cross-functional engineering teams, external partners, and key stakeholders while ensuring successful execution against technical, schedule, cost, and quality objectives. Depending on experience and project needs, the successful candidate may serve as the ASIC Chip Lead, owning technical execution, or as the Project Lead, owning overall program execution, or both. The ideal candidate combines strong technical depth with exceptional program leadership and has a proven track record delivering complex ASICs involving multiple internal teams, external vendors, and foundry partners.

Requirements

BSEE, MSEE, or equivalent with 15+ years of semiconductor industry experience and 5+ years leading complex ASIC developments.
Demonstrated success leading multiple complex mixed-signal ASICs through architecture, design, verification, tapeout, silicon bring-up, and production.
Experience managing geographically distributed teams and external design partners.
Strong program management skills, including schedule planning, risk management, and executive communications.
Proven ability to lead through influence across multiple engineering disciplines.
Experience with advanced-node ASIC development preferred.

Responsibilities

Accountable for successful ASIC execution from concept through production, including schedule, quality, cost, tapeout readiness, and first-pass silicon success.
Lead cross-functional teams including architecture, analog design, digital design, verification, physical design, package engineering, test, characterization, and operations.
Partner with system architects and engineering leaders to define ASIC architecture, technical tradeoffs, execution strategy, and product requirements.
Drive schedule development, critical-path management, milestone tracking, and risk mitigation.
Conduct regular program reviews and provide status updates to engineering and executive leadership.
Coordinate outsourced design partners, EDA vendors, IP suppliers, and foundry partners.
Resolve technical and program conflicts while balancing quality, cost, and schedule objectives.
Drive tapeout readiness reviews and silicon bring-up planning.
Develop staffing plans and identify resource gaps throughout the project lifecycle.