Senior Analog Layout Engineer

Apple•Cupertino, CA

10h•Onsite

About The Position

Apple Inc. is seeking a Senior Analog Layout Engineer to deliver Analog Mixed-Signal IP in a SOC flow. This role involves crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floor plans, and analyzing intricate circuits with circuit designers. The engineer will run complete sets of design verification tools, plan and schedule work, and coordinate vital layout tradeoffs. Responsibilities include interpreting LVS, DRC, ERC, EMIR, and PDV reports to optimize layout completion, delegating and coordinating tasks to contractors, and ensuring layout quality and on-time delivery. The role also entails participating in layout methodology and CAD initiatives to enhance efficiency and productivity, evaluating new advanced technology nodes, and collaborating with skilled teams to develop next-generation SOCs. The position is 40 hours/week and offers a base pay range of $168,583 - $213,700/yr, dependent on skills, qualifications, experience, and location.

Requirements

Bachelor’s degree or foreign equivalent in Electronic Engineering, Electronics and Communications, or a related field.
4 years of experience in the job offered or related occupation.
4 years of experience using tools to navigate and create project related technology config, workspace, LEF (Library Exchange Format).
4 years of experience performing snap design (release tool) on schematic and layout megacells.
4 years of experience actively participating in automation development activities.
4 years of experience writing spec for CAD to execute.
4 years of experience efficiently navigating, debugging and fixing EMIR (Electro-migration and Current/Resistance Drop) violations.
4 years of experience providing feedback to ESD (Electrostatic Discharge) and tech teams for enhancement requests.
4 years of experience conducting meaningful layout reviews.
4 years of experience setting priorities for block or megacells to meet quality and deadline for each milestones.
4 years of experience creating and analyzing RC (resistance & capacitance) extraction to debug and fix layout mismatches.
4 years of experience using and teaching Paragon X tool to others.
4 years of experience providing circuit designers with ways to improve schematics for layout implementation.
4 years of experience providing circuit designers with recommendations on technology impact (know what design rule checks (DRC) are possible or not).
4 years of experience debugging and fixing complex design rule check (DRC) and layout Vs. schematic (LVS) violations: Latch-up, ESD (Electrostatic Discharge), transistor hookup errors & short circuits.
4 years of experience creating various groups, width/Space patterns (WSP), toolbar, layout editor, layer manipulation, check in & check out data, XL (Cadence Extended Layout Suite) compliant.

Responsibilities

Deliver Analog Mixed-Signal IP in a SOC flow.
Craft sophisticated layouts for mixed-signal and analog circuits.
Review floor plans.
Analyze intricate circuits with circuit designers.
Run complete sets of design verification tools.
Plan/schedule work.
Coordinate vital layout tradeoffs.
Interpret LVS, DRC, ERC, EMIR, and PDV reports to find the fastest way to complete the layout, exceeding engineering specifications and expectations.
Delegate and coordinate tasks to a group of contractors.
Check the layout quality and its on-time delivery.
Participate in layout methodology and CAD initiatives to create innovative ways to boost layout efficiency and productivity.
Take part in evaluating the next breakthrough of new advanced technology nodes.
Collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCS.
Perform snap design (release tool) on schematic and layout megacells.
Actively participate in automation development activities.
Write spec for CAD to execute.
Efficiently navigate, debug and fix EMIR violations.
Provide feedback to ESD and tech teams for enhancement requests.
Conduct meaningful layout reviews.
Set priorities for block or megacells to meet quality and deadline for each milestone.
Create and analyze RC extraction to debug and fix layout mismatches.
Use and teach Paragon X tool to others.
Provide circuit designers with ways to improve schematics for layout implementation.
Provide circuit designers with recommendations on technology impact (know what design rule checks (DRC) are possible or not).
Debug and fix complex design rule check (DRC) and layout Vs. schematic (LVS) violations: Latch-up, ESD, transistor hookup errors & short circuits.
Create various groups, width/Space patterns (WSP), toolbar, layout editor, layer manipulation, check in & check out data, XL compliant.