Analog IC Layout Engineer
About The Position
We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team.
Requirements
- 2+ years of experience in analog and mixed-signal IC layout design
- 1+ year experience with FinFET technologies
- Ability to identify the best approach to solving problems
Nice To Haves
- Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
- Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
- Understanding on failure-prone circuit and layout structures
- Experience with analog DFM standards
- Experience with layout P-cell design and implementation
- Experience with layout automation
Responsibilities
- Crafting state-of-the-art layouts for mixed-signal and analog circuits
- Amplifiers
- Filters
- Switched capacitor circuits
- Oscillators
- Data converters
- Power management circuits
- Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
- Physical verification of custom IC mask layouts (LVS, DRC, ERC)
Benefits
- Excellent medical, dental, and vision insurance through a PPO plan
- Paid holidays
- Commuter benefits
- Meals provided
- Equity (RSUs)
- 401(k) plan
- Parental leave
- Flexible time off
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
Number of Employees
251-500 employees
