Senior Analog Design Engineer – Power & Clock IP
About The Position
The Senior Analog Design Engineer will develop power management and clocking IP for Treo-based SoCs. This is a hands-on contributor role responsible for owning complex analog blocks and collaborating with design, verification, validation, digital, and technology teams. The engineer will take analog IP from specification through silicon validation, including schematic design, layout review, post-layout verification, corner analysis, lab characterization, and post-silicon debugging. The role also includes documenting designs and developing reusable IP methodologies. The position uses industry-standard schematic capture and SPICE/AMS simulation tools. Design sign-off includes PVT, noise, jitter, reliability, and aging analysis. Scripting and automation techniques are applied to improve design efficiency and quality. Success is measured by on-time delivery of analog IP blocks, robust PVT coverage and high-quality silicon results, and strong cross-functional collaboration and technical execution.
Requirements
- At least 5 years of experience in analog IC design.
- Experience designing power management and/or clocking circuits.
- Solid understanding of analog circuit design, device physics, and layout effects.
- Proficiency with SPICE/AMS simulation and mixed-signal verification.
- Ability to work independently and communicate technical issues effectively.
Nice To Haves
- Experience with Verilog-A/AMS modeling.
- Exposure to automotive or industrial applications.
- Interest in AI-assisted design and automation workflows.
Responsibilities
- Design, simulate, and verify analog IP, including LDOs, DC/DC converters, charge pumps, PLLs, DLLs, and oscillators.
- Own analog blocks from specification through silicon validation.
- Perform schematic design, layout review, post-layout verification, and corner analysis.
- Collaborate with digital, validation, and technology teams during integration and bring-up.
- Support lab characterization and post-silicon debugging.
- Document designs and develop reusable IP methodologies.
- Use schematic capture and SPICE/AMS simulation tools.
- Perform PVT, noise, jitter, reliability, and aging analysis for design sign-off.
- Apply scripting and automation techniques to improve design efficiency and quality.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed
