RTL / Physical Design Engineer

Persimmons•San Jose, CA

About The Position

As a Persimmons RTL to PD Engineer, you will be responsible for high quality RTL drops to our PD Partners of next-generation AI silicon. Your primary duties and responsibilities include:

Requirements

Educational Foundation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
Proven Experience: 3+ years of hands-on RTL-to-PD implementation experience, with demonstrated success taking designs from synthesis through tapeout on real silicon.
Technical Mastery: Proficiency in SystemVerilog/Verilog and deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains, including all associated quality and sign-off checks.
Specialized Expertise: Strong command of static timing analysis and the ability to write timing constraints from scratch based on RTL-level design understanding.
Flow Innovation: Experience developing and maintaining scripted, automated design flows; exposure to AI-assisted automation tools is a strong plus.

Responsibilities

Own RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, upf and static checks. Ensuring designs meet quality, performance, power & area targets.
Drive timing closure by authoring precise timing constraints from RTL understanding, running static timing analysis & resolving setup violations across complex multi-corner environments.
Execute floorplanning and physical implementation using Cadence/Synopsys tools, making informed decisions on macro placement & tool options to optimize PPA.
Build and maintain scripted, automated design flows that streamline synthesis, analysis, and sign-off processes—leveraging AI agents and modern automation tools to accelerate iteration and reduce manual overhead.
Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend handoffs, enforce quality checks, and ensure seamless integration across the design hierarchy.
Contribute to advanced post DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration as scope demands.