RTL integration Engineer

Broadcom • San Jose, CA

1d

About The Position

The candidate will be required to perform IP integration and IP test/debug mode verification at the SoC level. This role involves creating RTL designs, performing linting, and executing CDC and RDC analysis for both RTL and gates. Additionally, the candidate will handle synthesis, palladium modeling, and STA support. Strong debugging skills are highly required.

Requirements

• Extensive knowledge of implementation, synthesis, and timing issues.
• Strong understanding of UVM and SystemVerilog.
• Deep familiarity with zero-delay and SDF simulations.
• Proven experience in gate-level simulation (GLS).
• Familiarity with Clock Domain Crossing (CDC) analysis for both RTL and gate-level designs.
• Ability to work independently with minimal supervision.
• Experience working within a global team and a dynamic environment.
• Strong ability to quickly learn and adapt to new tools and methodologies.
• Excellent communication skills.

Nice To Haves

• Highly desirable experience with simulation tools such as NCSim and VCS.

Responsibilities

• Perform IP integration and IP test/debug mode verification at the SoC level.
• Create RTL designs.
• Perform linting.
• Execute CDC and RDC analysis for both RTL and gates.
• Handle synthesis, palladium modeling, and STA support.
• Debug failures effectively.

Benefits

• Discretionary annual bonus
• Competitive new hire equity grant
• Annual equity awards
• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave
• Vacation time
• Paid Family Leave
• Other leaves of absence

What This Job Offers

• Job Type: Full-time
• Career Level: Senior