Sr. RTL Design Engineer

Advanced Micro Devices, Inc•San Jose, CA

4d•Hybrid

About The Position

As a key member of AMD’s FPGA Product and Platform development team, you will have various responsibilities in the technical execution of Adaptive & Embedded Computing Group (AECG) device programs from definition to productization. You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in supporting IP development for Silicon implementation and first-time-right SW solution. You are passionate about HW architecture, Digital design, and building cutting-edge silicon. As a strong problem solver and analytical thinker, you bring collaboration, communication, and adaptability to cross-functional teams spanning multiple time zones.

Requirements

Bachelor's or master’s degree in electrical engineering, computer engineering, or a related field.

Nice To Haves

Strong understanding of the complete ASIC/SoC development flow, from RTL architecture through physical implementation and silicon bring-up.
Strong RTL design and integration experience using Verilog and SystemVerilog.
Experience working with high-speed interfaces and complex IPs such as HBM, Die-to-Die (D2D), SerDes, PCIe, and memory subsystems.
Deep understanding of VLSI design principles, Design Automation methodologies, and IC development processes.
Working knowledge of physical design concepts including floorplanning, synthesis, place-and-route, timing closure, and Static Timing Analysis (STA).
Hands-on experience with industry-standard EDA tools such as Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, and Cadence tool suites.
Experience with UVM/OVM verification methodologies, testbench development, BFMs, simulation environments, and debug workflows.
Proven experience implementing DFT solutions for large-scale SoCs, including scan, compression, MBIST, LBIST, boundary scan, and related test technologies.
Familiarity with FPGA architectures and prototyping methodologies is a plus.
Strong scripting and automation skills using Perl, Tcl, Shell, Python, or similar languages.
Demonstrated ability to independently drive technical initiatives and solve complex engineering challenges.
Excellent written and verbal communication skills, with the ability to effectively collaborate across geographically distributed teams.
Proven ability to mentor engineers and contribute to technical leadership within an organization.

Responsibilities

Participate in all stages of the design flow, from RTL development through GDS implementation.
Design and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.
Support physical design activities, including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
Collaborate closely with Functional Verification teams to support block-level verification using constrained-random and directed test environments based on System Verilog and UVM.
Utilize scripting languages such as Perl, Tcl, Shell, and Python to maintain existing design automation flows and develop new tools supporting various aspects of design implementation.
Partner with cross-functional teams across multiple engineering disciplines and geographic locations.
Communicate regularly with global project teams to resolve technical issues and ensure project milestones and objectives are achieved.