RTL Design Engineer
About The Position
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, enabling everything from self-driving cars to AI-powered systems. We lead in chip design, verification, and IP integration, empowering innovators to create high-performance silicon and software solutions. Join us and help shape the future of technology. A highly experienced digital design engineer with deep expertise in PHY architecture and RTL development. You bring a strong foundation in high-speed interface technologies such as DDR and UCIe, combined with hands-on experience delivering complex ASIC designs from concept through implementation. You thrive in collaborative environments, enjoy solving challenging technical problems, and are passionate about developing innovative semiconductor solutions.
Requirements
- BS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience, or MS with 10+ years of experience.
- Strong experience in ASIC RTL design and digital logic development.
- Expertise in PHY design, DDRIO, UCIe, SERDES, or related high-speed interface technologies.
- Solid understanding of the complete SoC design cycle, from architecture through implementation.
- Experience with design verification methodologies and hardware debugging.
- Strong problem-solving, analytical, and communication skills.
Nice To Haves
- Experience developing complex IPs for advanced process technologies.
- Familiarity with low-power design techniques and clocking architectures.
- Experience mentoring engineers and leading technical projects.
- Knowledge of industry-standard EDA tools and design methodologies.
Responsibilities
- Architect, design, and develop high-performance digital logic for PHY, DDRIO, and UCIe-based solutions.
- Define and implement RTL architectures while working closely with verification, physical design, and system teams.
- Drive chip- and block-level design activities through all phases of the ASIC development cycle.
- Optimize designs for performance, power, area (PPA), and product scalability.
- Develop and evaluate complex physical IP solutions, including SERDES and DDR subsystems.
- Review designs and mentor engineers to ensure technical excellence and development best practices.
- Collaborate with cross-functional teams to deliver high-quality silicon solutions on schedule.
Benefits
- Comprehensive and competitive benefits package designed to support your health, wellbeing, and financial future.
- Annual bonus
- Equity
- Other discretionary bonuses
- Comprehensive health, wellness, and financial benefits
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What This Job Offers
Job Type
Full-time
Career Level
Senior
