Staff, RTL Engineer

Tenstorrent

11d•$100,000 - $500,000•Remote

About The Position

Tenstorrent is a leader in cutting-edge AI technology, aiming to revolutionize performance, ease of use, and cost efficiency. As AI redefines the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team has developed a high-performance RISC-V CPU from scratch and is passionate about AI and building the best AI platform. We value collaboration, curiosity, and solving hard problems. We are expanding our team and seeking contributors at all seniority levels to help build the next generation of AI and CPU hardware. This role involves driving microarchitecture and RTL development for cutting-edge digital IPs that power industry-leading AI/ML accelerators and CPUs, encompassing design, debug, test, and silicon bring-up. It offers a unique opportunity to shape groundbreaking hardware from concept to production while collaborating with top industry engineers. This role is remote and based out of North America or Taiwan. We welcome candidates at various experience levels, and the specific level will be determined during the interview process.

Requirements

Experienced RTL and microarchitecture engineer with a strong background in complex ASIC, SoC, or chiplet development.
Hands-on experience with Verilog-based design, industry-standard simulation and synthesis tools, and complex digital subsystem integration.
Skilled at solving challenging logic, debug, and system-level design problems across pre-silicon and post-silicon environments.
Effective collaborator who works closely with architecture, verification, physical design, DFx, and silicon validation teams.
Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
5+ years of relevant industry experience.
Strong understanding of microarchitecture development and industry-standard protocols such as AXI, AHB, APB, I3C, and SPI.
Proven debugging skills across both pre-silicon and post-silicon environments, including silicon bring-up and root-cause analysis.

Nice To Haves

Bonus experience with open-source hardware projects, DFT/DFD methodologies, scan test, MBIST, JTAG, SoC debug architectures, or RISC-V CPU cores.
Familiarity with DFT/DFD concepts, including scan test, MBIST, JTAG, ATPG, or chip-level debug architectures, is highly valued.

Responsibilities

Drive microarchitecture and RTL development for cutting-edge digital IPs powering industry-leading AI/ML accelerators and CPUs.
Work across design, debug, test, and silicon bring-up.
Design and implement RTL for complex digital subsystems, fabrics, debug and test subsystems, or SoC-level integrations.
Evaluate and optimize power, performance, and area (PPA) tradeoffs while delivering high-quality RTL.
Perform debugging across pre-silicon and post-silicon environments, including silicon bring-up and root-cause analysis.