Intern - Digital Design

Rambus•Johns Creek, GA

2d•Hybrid

About The Position

Rambus is seeking an RTL Digital Design Intern to join the Memory Interface Chip Business Unit’s engineering team in Johns Creek, Georgia. The intern will report to the Digital Design Director of Engineering and work with experienced engineers on an assignment within the DDR6 memory interface design team, developing silicon products for AI data centers. The role involves developing RTL for next-generation DDR5/DDR6 memory interface products and contributing to memory interface architectures and protocols. The intern will also work with engineering, verification, and validation teams on design analysis, timing closure, simulation, silicon bring-up, and debugging. Rambus describes its work environment as hybrid, with office-based employees encouraged to spend an average of at least three days per week onsite and up to two days working remotely.

Requirements

Currently pursuing a BS or MS in Electrical Engineering or Computer Engineering.
Relevant coursework in Digital Integrated Circuits, Advanced VLSI Systems, Advanced Computer Architecture, Embedded Systems, and Design and Analysis of Algorithms.
Background in digital RTL design, including standard LEC, CDC, Lint, DFT, BIST, and STA tools.
High aptitude with Verilog and SystemVerilog.
Ability to document design techniques, test, and verification methodologies.
Python or Perl scripting development skills.
Strong debugging, analytical, and communication skills.

Responsibilities

Develop Verilog/SystemVerilog RTL for next-generation DDR5/DDR6 memory interface products.
Learn and contribute to DDR5/DDR6 memory interface architectures and protocols.
Design digital control logic, state machines, and register interfaces.
Analyze and optimize RTL designs for power, performance, and area (PPA).
Support timing closure and Static Timing Analysis (STA).
Create behavioral models for simulation and verification.
Work with verification and validation teams during silicon bring-up and debugging.