Intern - Digital Design

Rambus•Johns Creek, GA

4d•Hybrid

About The Position

Rambus is seeking an RTL Digital Design Intern to join the Memory Interface Chip Business Unit engineering team in Johns Creek, Georgia. Reporting to the Digital Design Director of Engineering, the intern will work with experienced engineers on an assignment within the DDR6 memory interface design team, developing silicon products for AI data centers. The role focuses on next-generation DDR5/DDR6 memory interface design and offers a hybrid work environment. Office-based employees are encouraged to work onsite an average of at least three days per week, with up to two days remote. Rambus develops memory interface chips and Silicon IP for data center connectivity and data-intensive workloads. The company describes its culture as committed to respect, support, fairness, inclusion, and equitable access to opportunities and resources.

Requirements

Currently pursuing or holding a BS or MS in Electrical Engineering or Computer Engineering.
Coursework in Digital Integrated Circuits, Advanced VLSI Systems, Advanced Computer Architecture, Embedded Systems, and Design and Analysis of Algorithms.
Background in digital RTL design, including standard LEC, CDC, Lint, DFT, BIST, and STA tools.
High aptitude with Verilog and SystemVerilog.
Ability to document design techniques, test methodologies, and verification methodologies.
Python or Perl scripting development skills.
Strong debugging, analytical, and communication skills.

Responsibilities

Develop Verilog/SystemVerilog RTL for next-generation DDR5/DDR6 memory interface products.
Learn and contribute to DDR5/DDR6 memory interface architectures and protocols.
Design digital control logic, state machines, and register interfaces.
Analyze and optimize RTL designs for power, performance, and area (PPA).
Support timing closure and Static Timing Analysis (STA).
Create behavioral models for simulation and verification.
Work with verification and validation teams during silicon bring-up and debugging.