RTL Design Sign Off Lead
About The Position
We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be delivered to the SOC teams. In this role, you will be the technical authority responsible for defining and enforcing synchronization strategies across complex, multi-clock domains in advanced process nodes. You will own the constraint creation process for synthesis, full-chip CDC/RDC methodology, establishing rigorous constraints and waivers to ensure zero-defect silicon. You will collaborate closely with Architecture and Chip Lead teams to review the testability and DFT design, clocking and reset architectures early in the design cycle, identifying potential metastability or reset-glitch issues before RTL freeze. The ideal candidate has 8+ years of experience and a mastery of structural and functional verification of crossings using industry-standard tools (e.g., SpyGlass CDC/RDC, Spyglass Lint, JasperGold, or Meridian). Experience with high-speed interfaces such as SerDes, LPDDR5/6, DDR4/5 or HBM, where asynchronous boundaries are critical, is highly desired. As a Senior Engineer, you are expected to mentor the broader design team on Synthesis, DFT, CDC/RDC best practices and drive automated flows to streamline sign-off for multi-site global teams.
Requirements
- BSEE required
- 8+ years of related experience
- Mastery of structural and functional verification of crossings using industry-standard tools (e.g., SpyGlass CDC/RDC, Spyglass Lint, JasperGold, or Meridian).
Nice To Haves
- MSEE/PHD preferred
- Experience with high-speed interfaces such as SerDes, LPDDR5/6, DDR4/5 or HBM, where asynchronous boundaries are critical.
Responsibilities
- Define and enforce synchronization strategies across complex, multi-clock domains in advanced process nodes.
- Own the constraint creation process for synthesis.
- Develop and implement full-chip CDC/RDC methodology, establishing rigorous constraints and waivers.
- Collaborate with Architecture and Chip Lead teams to review testability and DFT design, clocking and reset architectures.
- Identify potential metastability or reset-glitch issues before RTL freeze.
- Mentor the broader design team on Synthesis, DFT, CDC/RDC best practices.
- Drive automated flows to streamline sign-off for multi-site global teams.
Benefits
- Discretionary annual bonus
- Competitive new hire equity grant
- Annual equity awards
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave
- Other leaves of absence
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What This Job Offers
Job Type
Full-time
Career Level
Senior
