The Digital Design RTL Engineer will operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off. This role involves close collaboration with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule. The ideal candidate will have high proficiency in SystemVerilog and a proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below). A deep understanding of PPA optimization, clock domain crossing (CDC) analysis, and low-power design techniques is essential.
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Job Type
Full-time
Career Level
Senior