RTL Design Engineer

Rambus • Montreal, QC

60d • Hybrid

About The Position

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Design Engineer to join our IP Engineering Logic Design team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.
As a Design Engineer, you will design synthesizable IP at the point of technology, for the latest PCIe, CXL standards.
Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.

Requirements

• Verilog and System Verilog
• Good English skills, communication skills, and willingness to work with an international team.

Nice To Haves

• Knowledge of UPF
• Knowledge of ASIC and FPGA design flow and tools (ASIC Synthesis, CDC / RDC / Linting, Quartus, Vivado)

Responsibilities

• Follow latest developments in PCIe standards
• Micro-architecture and design of advanced PCIe and CXL IP, for PCIe7 and beyond
• Participate in FPGA prototyping and hardware validation
• Run and improve quality checks (ASIC synthesis, CDC/RDC/Linting, simulation)
• Collaborate with a worldwide team
• Contribute to technical improvements on all aspects of the IP design domain

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed