Research Computer Scientist, Reconfigurable Computer Architecture

University of Southern California • Arlington, VA

13d • Onsite

About The Position

USC’s Information Sciences Institute (ISI), part of the Viterbi School of Engineering, is seeking a Research Computer Scientist for its Computational Systems and Technology Division. The role leads research and development in reconfigurable computer architectures, focusing on programmable compute and control structures that rapidly switch among signal-processing, communications, and related workloads while meeting throughput, latency, power, and resource constraints. The scientist will develop architectural concepts, models, and prototypes, guide implementation and evaluation across hardware and software, and collaborate with interdisciplinary teams to mature architectures for sponsored research and transition. Potential initial applications include adaptive communications and coding, a multifunction RF system on chip, or related efforts, depending on awards and program direction.

The position is part of the Reconfigurable Computing Group, which develops computing architectures from early concepts through FPGA demonstrations and custom silicon development. The group also develops tools for programming and verifying systems, including AI-assisted methods for hardware design, testing, device characterization, and debugging. The position is based in ISI’s Arlington, Virginia office.

The role provides technical direction to researchers, engineers, and students; coordinates architecture deliverables across collaborating organizations; documents work for sponsors; contributes to proposals, reports, publications, and presentations; and engages prospective transition partners on architecture requirements and evaluation.

Requirements

• Doctorate in computer engineering, electrical engineering, computer science, or a closely related field.
• Demonstrated research contributions in computer architecture or reconfigurable computing.
• Ability to reason across architecture and implementation, with experience in performance modeling, simulation, RTL design, FPGA prototyping, or related hardware development.
• Proficiency in Python or C++ for architecture modeling and evaluation.
• Working knowledge of Verilog, VHDL, or SystemVerilog for digital hardware prototypes.
• Strong technical writing, collaboration, and research leadership skills.
• Ability to handle Controlled Unclassified Information (CUI); eligibility requires U.S. citizenship or permanent residency under U.S. government regulations.
• Demonstrated record of outstanding research contributions and experience.
• Proven technical proficiency, creativity, successful collaboration, and independent thought.
• Strong managerial skills.
• Ability to conceptualize research directions, exert technical leadership, communicate technical ideas, coordinate contributions to a research program, and present research plans and results to elicit favorable funding actions.

Nice To Haves

• Five or more years of relevant research experience.
• Expertise in coarse-grained reconfigurable arrays, heterogeneous or domain-specific accelerators, RISC-V or Arm processors, high-bandwidth interconnects, high-speed I/O, or hardware-software co-design.
• Experience with RF or DSP workloads, error-control coding, communication systems, ASIC development, verification, compiler or runtime integration, or sponsor-funded research.
• Familiarity with FPGA and ASIC implementation and verification tools, such as Vivado, Verilator, or commercial EDA flows.
• Experience applying AI coding assistants or agents to Verilog, VHDL, or SystemVerilog development, verification, or hardware design exploration.
• Nationally recognized reputation for excellence in area of expertise.

Responsibilities

• Define and evolve reconfigurable architectural components, including processing elements, configurable compute fabrics, control and scheduling mechanisms, on-chip communication, memory and data movement, and external-system interfaces.
• Formulate research questions and conduct trade studies concerning rapid reconfiguration, determinism, throughput, energy efficiency, scalability, and programmability.
• Develop performance models and publishable technical results.
• Lead architecture modeling, RTL and FPGA prototyping, integration, verification, and benchmarking with hardware, compiler, software, and application researchers.
• Investigate AI-assisted and agent-based methods for HDL design, testbench generation, and design exploration, and verify generated artifacts against functional and performance requirements.
• Establish representative workloads and measurable requirements, analyze bottlenecks, and guide design changes.
• Support application demonstrations, such as adaptive encoding and decoding workflows or multifunction RF signal processing, as program needs warrant.
• Provide technical direction to researchers, engineers, and students.
• Coordinate architecture deliverables across collaborating organizations.
• Document designs and results for sponsors, and contribute to proposals, reports, publications, and presentations.
• Engage prospective transition partners regarding architecture requirements and evaluation.

Benefits

• Work on exciting and engaging projects with real-world impact.
• Contribute across the full project lifecycle in a small-team environment.
• Workplace that supports a quality work-life balance.
• Access to opportunities for top-tier university education for the employee and their children.
• Comprehensive benefits, including medical coverage and matched retirement contributions.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Ph.D. or professional degree