Research Computer Scientist, Reconfigurable Computer Architecture
About The Position
USC’s Information Sciences Institute (ISI), part of the Viterbi School of Engineering, is seeking a Research Computer Scientist for its Computational Systems and Technology Division. The position leads research and development in reconfigurable computer architectures, focusing on programmable compute and control structures that can rapidly switch among signal-processing, communications, and related workloads while meeting demanding throughput, latency, power, and resource constraints. The scientist develops architectural concepts, models, and prototypes; guides implementation and evaluation across hardware and software; and works with interdisciplinary teams to mature architectures for sponsored research and transition. Potential applications include adaptive communications and coding, a multifunction RF system on chip, and related efforts, depending on awards and program direction. The Reconfigurable Computing Group develops computing systems from early architectural concepts through FPGA demonstrations and custom silicon development. It also develops tools for programmable and verifiable systems, including AI-assisted methods for hardware design, testing, device characterization, and debugging. The position is based in ISI’s Arlington, Virginia office.
Requirements
- Doctorate in computer engineering, electrical engineering, computer science, or a closely related field.
- Demonstrated research contributions in computer architecture or reconfigurable computing.
- Ability to reason across architecture and implementation, with experience in performance modeling, simulation, RTL design, FPGA prototyping, or related hardware development.
- Proficiency in Python or C++ for architecture modeling and evaluation.
- Working knowledge of Verilog, VHDL, or SystemVerilog for digital hardware prototypes.
- Strong technical writing, collaboration, and research leadership skills.
- Ability to handle Controlled Unclassified Information (CUI); eligibility requires U.S. citizenship or permanent residency.
- Demonstrated record of outstanding research contributions and experience; technical proficiency, creativity, collaboration, independent thought, and managerial skills.
- Demonstrated ability to conceptualize research directions, provide technical leadership, communicate technical ideas, coordinate contributions to a research program, and present research plans and results to support funding actions.
Nice To Haves
- Five or more years of relevant research experience.
- Expertise in coarse-grained reconfigurable arrays, heterogeneous or domain-specific accelerators, RISC-V or Arm processors, high-bandwidth interconnects, high-speed I/O, or hardware-software co-design.
- Experience with RF or DSP workloads, error-control coding, communication systems, ASIC development, verification, compiler or runtime integration, or sponsor-funded research.
- Familiarity with FPGA and ASIC implementation and verification tools, such as Vivado, Verilator, or commercial EDA flows.
- Experience applying AI coding assistants or agents to Verilog, VHDL, or SystemVerilog development, verification, or hardware design exploration.
- Nationally recognized reputation for excellence in area of expertise.
Responsibilities
- Define and evolve reconfigurable architectural components, including processing elements, configurable compute fabrics, control and scheduling mechanisms, on-chip communication, memory and data movement, and external-system interfaces.
- Formulate research questions and conduct trade studies involving rapid reconfiguration, determinism, throughput, energy efficiency, scalability, and programmability.
- Develop performance models and publishable technical results.
- Lead architecture modeling, RTL and FPGA prototyping, integration, verification, and benchmarking in collaboration with hardware, compiler, software, and application researchers.
- Investigate AI-assisted and agent-based methods for HDL design, testbench generation, and design exploration, and verify generated artifacts against functional and performance requirements.
- Establish representative workloads and measurable requirements, analyze bottlenecks, and guide design changes.
- Support application demonstrations such as adaptive encoding and decoding workflows or multifunction RF signal processing, as program needs warrant.
- Provide technical direction to researchers, engineers, and students.
- Coordinate architecture deliverables across collaborating organizations.
- Document designs and results for sponsors; contribute to proposals, reports, publications, and presentations.
- Engage prospective transition partners regarding architecture requirements and evaluation.
Benefits
- Opportunities to work on engaging projects with real-world impact.
- Opportunity to contribute across the full project lifecycle in a small-team environment.
- Workplace that supports quality work-life balance.
- Access to opportunities for top-tier university education for employees and their children.
- Comprehensive benefits, including medical coverage and matched retirement contributions.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
Ph.D. or professional degree
