R&D IC Design Engineer

Broadcom•San Jose, CA

About The Position

This opening is for working on chips that enable Physical Layer Products for High Speed Optical Communication. The role involves architecting block-level design specifications from marketing and/or system requirements, preparing detailed design documents and timing constraint files, and performing RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate-level simulations, and silicon debug. The engineer will also be responsible for scripting various IC design tasks, preparing block-level resource requirements and development schedules, generating verification and test plans, performing design tradeoff analysis (leakage, dynamic power, die size, schedule, resource, priority, etc.), and silicon bring-up and validation, including ATE program bring-up.

Requirements

B.S degree in EE or computer Engineering. Minimum of 8 years of work experience with direct related technical skill
M.S degree/Ph.D in EE or Computer Engineering with 6 years of work experience.
Good knowledge of ARM subsystem
Good knowledge of high speed digital circuit design.
Good knowledge of digital upsampling/downsampling
Good knowledge of 10G/100G/200G/400G/800G Ethernet and OTN network.
Good knowledge on FEC (Forward Error Correction) design.
Strong analytical and problem solving skills as well as hands-on lab debugging experiences
Good knowledge of RTL simulation and synthesis.
In-depth knowledge for design for low power and design for test and design for manufacturing.
Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix/Perl Scripting or Python, and C.
Self-motivated, excellent communication skills and ability to excel in a team environment.
Good organization skills, able to follow through & bring issue to closure
Understand the entire IC development flow & procedure including silicon volume production qualification requirements & procedures
Enthusiastic & enjoy IC development works
Be able to work with teams at remote locations with different time zone.

Nice To Haves

Good knowledge of digital signal processing and error correction code is a plus

Responsibilities

Architect block level design specifications from the marketing requirements and/or system requirements
Prepare detailed design document, timing constraint file
RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate level simulations & silicon debug
Scripting for various IC design tasks such as STA, equivalency checks, test bench, simulations, synthesis, etc.
Prepare block level resource requirements & development schedule
Generate verification & test plans for design validation
Perform design tradeoff analysis – leakage, dynamic power, die size, schedule, resource, priority, etc.
Silicon bring up and validation, ATE program bring up