Product Engineer I - II or Sr. Product Engineer, Texas Institute for Electronics

The University of Texas at Austin • Austin, TX

1d • Onsite

About The Position

The Texas Institute for Electronics (TIE) is a public-private partnership focused on advancing semiconductor manufacturing in the U.S. We are developing cutting-edge equipment and processes for advanced packaging, logic, memory, heterogeneous integration, and chip cooling. TIE is part of The University of Texas at Austin's Cockrell School of Engineering, a leading institution in technology innovation and engineering education. The university offers a dynamic environment with extensive resources and a strong emphasis on research and academic excellence. This role is crucial for achieving TIE's goals of restoring U.S. leadership in semiconductor manufacturing.

Requirements

• Product Engineer I: Bachelor’s degree in Electrical Engineering, Semiconductor Physics, Computer Science, Materials Science or relevant field.
• Product Engineer II: Bachelor’s degree in Electrical Engineering, Semiconductor Physics, Computer Science, Materials Science, and a minimum of three years of relevant industry experience.
• Senior Product Engineer: Bachelor’s degree in Electrical Engineering, Semiconductor Physics, or Materials Science, and a minimum of ten years of relevant industry experience.
• Strong understanding of semiconductor device physics and mixed signal IC behaviors.
• Proficient programming skills in languages such as Python, MATLAB, C/C++, or Perl… for data analysis, and automation.
• Strong communication and teamwork skills, with the ability to collaborate effectively with cross-functional teams.
• Excellent analytical and problem-solving skills, as well as attention to detail.
• Ability to thrive in a fast-paced environment and manage multiple projects simultaneously.
• (Eng II or Senior): Prior experience in semiconductor design, product engineering, process Integration/manufacturing, Test, or packaging required.
• Relevant education and/or industry experience may be substituted as appropriate.
• Applicants must be authorized to work in the United States on a full-time basis for any employer without sponsorship.

Nice To Haves

• Master’s degree or PhD in semiconductor engineering fields such as Electrical Engineering, Materials Science, Semiconductor Physics or other relevant disciplines.
• Experience or Interest in (for entry level) at least one of the following areas: IC/Micro-system Design, Product Validation, Test, Process or wafer fab Integration, Semiconductor Packaging manufacturing, Thermal/stress optimization, and/or quality assurance, ATE and/or Bench validation of IC’s or process test structures, Semiconductor Failure analysis. (SEM/CSAM experience…), Materials packaging/stress/strain evaluations and process controls, Data analytics using scripting/programming putting results into tables/graphs/reports. (JMP, Power BI, Excel…), BIST definition and/or validation. Design & TEST BKM, and Apps engineering / Micro-system Product definition and requirements.
• Experience in a startup or research and development (R&D) environment.

Responsibilities

• Product and test vehicle validation to specifications.
• Development and optimization of manufacturing/test workflows.
• 2.5D/3D modeling accuracies.
• Creation of BKM’s (Best Known Practices) to comprehend and optimize Power/Thermal/Mechanical/Signal Integrity/RF impacts of multi-chiplet and multi-domain heterogeneous micro-systems.
• Contribute to the design and development of 2.5D & 3D advanced packaging solutions for semiconductor devices.
• Develop and support TIE's 3D-ADK (Assembly Design Kit).
• Interpret fab metrology, defect, E-test yield, and evaluate silicon-to-simulation correlation accuracies to understand and quantify process variations and their impacts on performance, yield, and reliability.
• Drive corrective actions across cross-functional teams to fix and identify root-cause systematic yield and reliability issues.
• Perform Failure analysis on products manufactured at TIE.
• Collaborate with internal and external design teams to ensure package compatibility with semiconductor die and system-level requirements.
• Design and execute appropriate DOE’s.
• Stay current with industry trends and emerging technologies in semiconductor packaging and design integration to drive innovation and continuous improvement.
• Define product DFT & DFM requirements and methodologies.
• Help with ATE Test plan definitions and requirements.
• Bench/lab validation and characterization of various IC solutions and test structures to understand multi-physics impacts of our 3DHI processes.
• Leverage data analytics to drive product yield and reliability optimization.
• Own entire product life cycle from bring up, performance/yield/reliability optimization, to customer qualification.
• Collaborate with customers to understand and resolve field failures.

Benefits

• Competitive health benefits (employee premiums covered at 100%, family premiums at 50%)
• Voluntary Vision, Dental, Life, and Disability insurance options
• Generous paid vacation, sick time, and holidays
• Teachers Retirement System of Texas, a defined benefit retirement plan, with 7.75% employer matching funds
• Additional Voluntary Retirement Programs: Tax Sheltered Annuity 403(b) and a Deferred Compensation program 457(b)
• Flexible spending account options for medical and childcare expenses
• Robust free training access through LinkedIn Learning plus professional conference opportunities
• Tuition assistance
• Expansive employee discount program including athletic tickets.
• Free access to UT Austin's libraries and museums with staff ID card
• Free rides on all UT Shuttle and Austin CapMetro buses with staff ID card
• Relocation assistance may be available.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level