Principal Validation Engineer

Microsoft•Mountain View, CA

3d•$142,800 - $274,800

About The Position

Microsoft’s Artificial Intelligence Silicon Engineering team is seeking a Principal Validation Engineer to join its Artificial Intelligence System on Chip (AISoC) Silicon team. The team develops high-performance, efficient AI silicon designs. This role focuses on silicon bring-up, electrical and functional validation, and lab infrastructure development for next-generation AI silicon, supporting execution from first silicon through product readiness. The engineer will work across silicon validation, board design, electrical engineering, FPGA prototyping, and system integration. The position calls for strong post-silicon validation experience, hands-on expertise with hardware platforms and board-level debugging, and experience with electrical engineering and lab operations. The role also involves cross-functional collaboration, improving validation processes, and mentoring engineers. Candidates must meet Microsoft, customer, and/or government security screening requirements, including a Microsoft Cloud Background Check at hire or transfer and every two years thereafter. The role requires access to export-controlled information. As a condition of employment, the successful candidate must provide proof of citizenship, U.S. residency, or another protected status for eligibility assessment; citizenship will be verified with a valid passport, with other documents applicable for lawful permanent residents, refugees, and asylees. The typical U.S. base pay range is $142,800–$274,800 per year. The range for specific work locations in the San Francisco Bay Area and New York City metropolitan area is $188,000–$304,200 per year. Certain roles may be eligible for benefits and other compensation. The position will be open for at least five days, with applications accepted on an ongoing basis until filled. Microsoft is an equal opportunity employer and provides information about requesting religious or disability accommodations during the application process.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 3 years of technical engineering experience; or a master's degree in one of these fields and at least 6 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 8 years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check.
Ability to provide documentation establishing eligibility to access export-controlled information, as described in the posting.

Nice To Haves

At least 10 years of related technical engineering experience; or a bachelor's degree in a relevant field and at least 4 years of technical engineering or internship experience; or a master's degree in a relevant field and at least 3 years of technical engineering or internship experience; or a doctorate in a relevant field.
At least 10 years of pre-silicon and post-silicon validation experience, with a record of delivering high-performance CPUs, vector processors, GPUs, or relevant products.
Experience leading validation lab planning, deployment, operation, and scaling.
Experience with PCB design flows, schematic capture, signal integrity, power integrity, and board manufacturing processes.
Experience supporting multiple silicon product cycles from platform definition through production.
Understanding of power delivery networks, voltage regulators, clocking architectures, and thermal systems.
Experience driving cross-functional execution with electrical engineering, mechanical engineering, firmware, design, architecture, and validation teams.
Excellent communication, leadership, and problem-solving skills.

Responsibilities

Bring up and validate complex AI SoCs, FPGA prototypes, and hardware platforms.
Drive board-level debugging and root-cause analysis across silicon, firmware, power delivery, clocks, resets, and high-speed interfaces.
Partner with PCB, package, power, mechanical, signal integrity, design, verification, and architecture teams to develop and validate hardware platforms.
Review schematics, PCB layouts, power architecture, and board designs for robust validation and bring-up readiness.
Define and execute electrical characterization plans, including power, thermal, margining, and high-speed interface validation.
Develop validation strategies, test plans, firmware, and automation infrastructure for pre-silicon and post-silicon environments.
Architect, deploy, and maintain validation labs, including rack infrastructure, FPGA platforms, automation frameworks, and lab instrumentation.
Use lab equipment to debug complex hardware and system issues.
Drive system integration and debugging across PCIe, Ethernet, DDR/HBM, JTAG, I2C, SPI, UART, and other platform interfaces.
Collaborate with cross-functional teams to influence next-generation silicon, board, and platform designs.
Improve validation efficiency through innovative debugging methodologies, automation, and lab workflows.
Mentor engineers in hardware bring-up, lab debugging, electrical engineering fundamentals, and validation methodologies.