Principal Validation Engineer

Microsoft•Mountain View, CA

22h•$142,800 - $304,200

About The Position

The Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team is seeking a Principal Validation Engineer to support next-generation AI silicon. The role focuses on silicon bring-up, electrical and functional validation, and laboratory infrastructure development. It spans silicon validation, board design, electrical engineering, FPGA prototyping, and system integration, supporting execution from first silicon through product readiness. The engineer will perform hands-on post-silicon validation, hardware-platform work, electrical engineering, board-level debugging, and lab operations. The position also involves cross-functional collaboration, developing validation and automation approaches, and mentoring engineers. The role requires passing Microsoft’s Cloud Background Check and verification of citizenship or other eligible status for access to export-controlled information.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 3 years of technical engineering experience; or a master’s degree in one of these fields and at least 6 years of technical engineering experience; or a bachelor’s degree in one of these fields and at least 8 years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Ability to provide proof of citizenship, U.S. residency, or other protected status for assessment of eligibility to access export-controlled information; citizenship will be verified with a valid passport, with other applicable documents permitted for lawful permanent residents, refugees, and asylees.

Nice To Haves

10 or more years of related technical engineering experience.
10 or more years of pre-silicon and post-silicon validation experience, with a record of delivering high-performance CPUs, vector processors, GPUs, or relevant products.
Experience leading validation lab planning, deployment, operation, and scaling.
Experience with PCB design flows, schematic capture, signal integrity, power integrity, and board manufacturing processes.
Experience supporting multiple silicon product cycles from platform definition through production.
Understanding of power delivery networks, voltage regulators, clocking architectures, and thermal systems.
Experience driving cross-functional execution with electrical engineering, mechanical engineering, firmware, design, architecture, and validation teams.
Excellent communication, leadership, and problem-solving skills.
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 4 years of technical engineering or internship experience; or a master’s degree in one of these fields and at least 3 years of technical engineering or internship experience; or a doctorate in one of these fields.

Responsibilities

Bring up and validate complex AI SoCs, FPGA prototypes, and hardware platforms.
Drive board-level debugging and root-cause analysis across silicon, firmware, power delivery, clocks, resets, and high-speed interfaces.
Partner with PCB, package, power, mechanical, signal integrity, design, verification, and architecture teams to develop and validate hardware platforms.
Review schematics, PCB layouts, power architecture, and board designs for validation and bring-up readiness.
Define and execute electrical characterization plans covering power, thermal behavior, margining, and high-speed interfaces.
Develop validation strategies, test plans, firmware, and automation infrastructure for pre-silicon and post-silicon environments.
Architect, deploy, and maintain validation labs, including rack infrastructure, FPGA platforms, automation frameworks, and lab instrumentation.
Use lab equipment to debug complex hardware and system issues.
Drive system integration and debugging across PCIe, Ethernet, DDR/HBM, JTAG, I2C, SPI, UART, and other platform interfaces.
Collaborate with cross-functional teams to influence next-generation silicon, board, and platform designs.
Improve validation efficiency through debugging methodologies, automation, and lab workflows.
Mentor engineers in hardware bring-up, lab debugging, electrical engineering fundamentals, and validation methodologies.