Principal SOC Power Architect

Advanced Micro Devices, Inc•Austin, TX

10h•Hybrid

About The Position

We are looking for a driven and diligent power architect to join the SOC Architecture team in the AMD Computing and Graphics group. Power architects guide SoCs from early concept stages through design execution and post silicon. This role involves collaboration with many teams across including SoC architecture definition, IP design, integration/ physical design, platform architecture, software, firmware, packaging, and silicon validation. If you wish to change the world by driving innovation for industry leading power performance and battery life on AMD’s Client and handheld products, this is the right opportunity for you.

Requirements

The candidate should have strong analytical thinking and problem-solving skills with excellent attention to detail.
The candidate must be organized, self-motivated and able to work effectively on teams large and small across multiple sites.
He or she must be able to prioritize assignments and drive them to completion.
Strong verbal and written communication skills are essential for driving technical discussions to successful and actionable outcomes.
Bachelor’s or Master’s degree in related discipline preferred
Several years of relevant, commercial experience

Nice To Haves

Architect with deep understanding of semiconductor power architecture and power delivery including on-die, substrate, silicon interposer and PCB power delivery.
Experience with power integrity/ signal integrity analysis, droop management/mitigation and capacitor types and performance.
Experience defining and analyzing workloads, system bottlenecks and optimizing computing systems for performance and power efficiency
Experience with architecting new SOC power features and low power states for improving battery life and guide prototyping the features.
Adept at power evaluation, modeling, simulation and silicon attainment
Demonstrated ability to co-own power feature enablement working with Firmware algorithm and software driver teams
Demonstrated ability to write detailed internal and customer facing architecture specifications.
C/C++ programming, automation & scripting languages, Excel, and software engineering concepts desirable
General familiarity with microprocessor and/or PC architecture
Self-driven individual, having ability to work independently to tackle complex cross discipline problems. Clear methodical problem solver bridging and collaborating across a world-wide team.

Responsibilities

As a technical member of the power architecture group, work with internal and external strategic partners, customers and industry standards to define AMD power roadmap and competitive targets for bounding box workloads.
Work involves detailed workload analysis to identify high value opportunities in IP, subsystem and SOC to increase power efficiency wrt performance/watt and battery life.
Detail oriented visionary, who can make clear process/flow recommendations and technically drive deployment across teams to achieve power bounding box targets.
Coordinate with world-wide teams including SOC architects, SOC and IP design teams, Systems engineering and Product Engineering to ensure power feature full realization from concept, to implementation, verification, FW/SW enablement, emulation and Silicon attainment.
Lead team in modeling complex power use case scenarios across SoC roadmap, correlating power estimates with pre-silicon model updates at each SOC maturity milestone to final tape-out PTPX numbers, real life workload correlation in emulation as well as post silicon, and ensure aggressive power objectives and goals are met for customer delivery.
Create innovative power reduction initiatives and methodologies and drive cross-organization alignment with SoC and IP teams for implementation towards power convergence.
Drive the framework for workload classification between HW/FW/OS.
Responsible for leading modeling design of experiments towards long-term integrated power-performance framework for driving power-perf improvements, voltage margining, feature ROI analysis and architectural solutions.
Define, align, and drive power feature definitions with cross-BU synergy in close collaboration with SoC and power architects.
Optimize PC use cases in terms of absolute power and in relative performance per watt.