Principal SoC Design Engineer

GlobalFoundries•Richardson, TX

1d•$153,000 - $265,000

About The Position

The Principal SoC Design Engineer provides deep technical expertise in developing high-performance data processing units and automotive microcontrollers with 8-10+ years of experience. This individual contributor role drives end-to-end SoC design—from architecture definition and micro-architecture specification to RTL implementation, optimization, and silicon-proven delivery—while advancing design methodologies for complex, safety-critical systems.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.
8-10+ years of hands-on experience in SoC/IP design for high-volume or safety-critical applications, including architecture-to-silicon delivery.
Expert-level proficiency in synthesizable SystemVerilog/Verilog, with deep knowledge of advanced digital design techniques (pipelining, FSM optimization, low-power design).
Strong command of SoC interconnects and protocols including AXI4/5, AHB, APB, CHI, and NoC fabrics.
Proven track record of leading RTL development for complex blocks (processors, accelerators, peripherals) on advanced nodes (7nm and below).
Proficiency in scripting (Python, Tcl, Perl) for RTL generation, automation, and design space exploration.
Exceptional analytical, problem-solving, and debugging skills for resolving ambiguous, cross-domain challenges.
Outstanding technical communication skills for presenting designs to stakeholders and documenting specifications.

Nice To Haves

Experience with RISC-V, ARM Cortex-A/R/M-series, or MIPS architectures in automotive or embedded applications.
Deep expertise in Functional Safety (ISO 26262 ASIL-D), including safety mechanisms, fault injection, and certification flows.
Familiarity with register description languages (IP-XACT, SystemRDL) and UVM-based verification methodologies.
Hands-on experience with high-performance data processing units (e.g., DSPs, AI accelerators, vision pipelines).
Proven technical leadership in driving design methodology evolution and tool adoption (Synopsys DC, Genus, Verdi).

Responsibilities

Lead gathering, analysis, and translation of complex subsystem, module, and SoC-level requirements into actionable micro-architecture specifications that meet stringent performance, power, and area targets.
Architect and develop synthesizable RTL (SystemVerilog/Verilog) for high-performance IP modules, subsystems, and full SoC integrations, including custom data processing units and automotive MCU cores.
Drive front-end design flow improvements, including automation of spec-to-RTL generation, IP reuse strategies, and advanced synthesis methodologies to boost team productivity and design quality.
Perform detailed RTL design reviews, optimization for timing/power/area, and constraint development to ensure first-pass silicon success across advanced nodes.
Champion design innovation by evaluating and integrating emerging standards, bus fabrics (AXI5/CHI, AMBA), and processor architectures (RISC-V, ARM Cortex) into production flows.
Collaborate deeply with architecture, verification, physical design, DFT, and software teams to resolve multi-disciplinary issues, define interfaces, and align on system-level tradeoffs.
Provide technical guidance through code reviews and knowledge sharing on best practices for maintainable, verifiable RTL.
Analyze silicon bring-up results, debug field issues, and implement lessons learned to refine design methodologies and IP libraries.
Collaborate with cross-functional teams (Architecture, Verification, Physical Design, etc.) to identify and resolve design issues.