SoC Design Engineer

Intel Corporation•Austin, TX

2d•$122,440 - $232,190•Hybrid

About The Position

As a SoC Logic Design Engineer, you will play a pivotal role in shaping the future of Intel's cutting-edge System on Chip (SoC) designs. This role offers an exciting opportunity to contribute to the development of world-class technology solutions that drive innovation across diverse industries. You will be responsible for developing high-quality logic designs, coding register transfer level (RTL) models, and performing thorough simulations to ensure optimal functionality. Your contributions will directly impact the success of Intel's products by enabling power-efficient, high-performance, and scalable solutions that meet or exceed market demands.

Requirements

Demonstrated ability to work collaboratively across teams and communicate effectively in complex technical environments
Passion for innovation, problem-solving, and continuous learning within the field of SoC design
Bachelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related field
3+ years of experience in microarchitecture development, RTL coding, or logic design
Experience in clock domain crossing techniques, low-power design methodologies, and SoC clocking structures
Experience with tools and strategies for RTL design, SoC integration, and physical implementation optimization

Nice To Haves

Master's degree in Electrical Engineering, Computer Engineering, or in a STEM related field.
Experience with secure development practices for secure design implementation.
Experience in SoC Builder and Network-on-Chip (NoC) architectures.

Responsibilities

Develop logic designs and RTL code for SoC designs, ensuring alignment with architectural and microarchitectural specifications
Perform integration of logic for IP blocks and subsystems into full-chip SoC designs
Conduct quality checks across various logic design aspects, including RTL, timing, power, and area convergence, and address design integrity for physical implementation
Optimize logic designs to meet stringent power, performance, area, and timing goals
Review verification plans and ensure the correctness of tested design features
Resolve RTL test failures by implementing corrective measures to ensure design feature correctness
Apply secure development practices to mitigate security threats and meet secure design objectives
Collaborate with IP providers to integrate and validate IP at the SoC level
Drive compliance with quality assurance standards to enable seamless IP/SoC handoffs