Principal SerDes Design Engineer

Celero Communications•San Jose, CA

About The Position

We are looking for a SerDes Lead Designer to deliver high-speed interconnect technology for next-generation AI. The role involves architecting and designing SerDes for next-generation transceivers, from system modeling and circuit design through lab validation, silicon correlation, and system-level performance optimization.

Requirements

  • Master’s degree and/or PhD in Electrical Engineering or a related field.
  • 10+ years of relevant experience in SerDes design.
  • Proven record of taking high-speed SerDes designs through tape-out and volume production.
  • Experience with lab bring-up, characterization, and debugging of designs that reach production.
  • Extensive experience with advanced node technologies, including 16nm/12nm, 7nm, 5nm, 3nm, or 2nm processes.
  • Prior cross-functional experience delivering IP and ensuring seamless integration in SoCs.
  • Strong communication and documentation skills.

Responsibilities

  • Define architecture, specifications, and circuit topologies for next-generation SerDes.
  • Oversee development of system-level behavioral models using tools such as MATLAB, SystemVerilog, and Verilog-A to analyze link budgets, equalization strategies, and jitter budgets.
  • Design high-performance analog and mixed-signal circuits in advanced process technologies.
  • Develop and oversee critical blocks, including RX/TX equalization (CTLE, DFE), high-speed PLLs, phase interpolators, DLLs, and TDCs.
  • Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve power, performance, and area.
  • Oversee physical layout to minimize parasitics, device stress, electromigration, and process-variation impacts.
  • Oversee signal-integrity and power-integrity analysis to meet system-defined targets.
  • Lead lab validation, debugging, and characterization of SerDes IPs.
  • Correlate silicon measurements with simulated data and lead performance optimization in the system environment.
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