Principal SerDes Design Engineer

Celero Communications•Irvine, CA

16h

About The Position

We are seeking a SerDes Lead Designer to architect and design SerDes for next-generation transceivers, delivering high-speed interconnect technology for next-generation AI. The role covers SerDes architecture and specifications, system-level modeling, analog/mixed-signal circuit design, physical design oversight, signal and power integrity analysis, and lab validation and optimization of SerDes IPs.

Requirements

Master’s degree and/or PhD in Electrical Engineering or a related field.
10+ years of relevant SerDes design experience.
Proven record of taking high-speed SerDes designs through tape-out and into volume production.
Experience with lab bring-up, characterization, and debugging of designs that reach production.
Extensive experience with advanced node technologies, including 16nm/12nm, 7nm, 5nm, 3nm, or 2nm processes.
Strong communication and documentation skills.

Responsibilities

Define architecture, specifications, and circuit topologies for next-generation SerDes.
Oversee development of system-level behavioral models using tools such as MATLAB, SystemVerilog, and Verilog-A to analyze link budgets, equalization strategies, and jitter budgeting.
Design high-performance analog and mixed-signal circuits in advanced node technologies.
Develop and oversee design of critical blocks, including RX/TX equalization (CTLE, DFE), high-speed PLLs, phase interpolators, DLLs, and TDCs.
Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve power, performance, and area.
Oversee physical layout to minimize parasitics, device stress, electromigration, and process-variation impacts.
Oversee signal integrity and power integrity analysis to achieve system-defined targets.
Lead lab validation, debugging, and characterization of SerDes IPs.
Correlate silicon measurements with simulated data and lead performance optimization in the system environment.
Work cross-functionally to deliver IP and ensure seamless integration in SoCs.