SerDes Application Design Expert

Advanced Micro Devices, Inc•San Jose, CA

1d•Hybrid

About The Position

The AMD SCIO (SerDes, Communication, I/O and Optical) team is seeking a versatile SerDes Engineer to drive the applications, firmware, and validation of our next-generation high-speed serial interface IP across both electrical and optical domains. In this role you will bridge SerDes IP design teams and SoC/system integrators, develop the low-level firmware that controls high-speed electrical SerDes and silicon photonics, and architect the characterization and validation solutions that take PCIe, Ethernet, and optical links from first silicon through volume production. You will collaborate closely with Product Development Groups, Silicon Design, DFT, Packaging, firmware, SI/PI, and key technology partners to ensure best practices and new test concepts are architected, developed, and driven throughout the organization.

Requirements

Self-motivated engineer with strong system intuition and a hands-on mindset
Equally comfortable working close to hardware and collaborating across firmware, electrical, and optical disciplines
Thrive in fast-paced, technically challenging environments
Excel in teamwork
Possess strong communication skills
Skilled in optimizing SerDes performance
Capable of identifying and addressing issues within a collaborative team environment
Working independently as well as alongside engineers across AMD design, verification, and validation teams

Nice To Haves

Knowledge of physical-layer specifications and industry standards such as PCIe, IEEE 802.3 Ethernet, and OIF
Experience in producing quality firmware for mixed-signal systems
Hands-on experience with full-stack lab instruments such as high-speed scopes, BERT, VNA, and other associated lab equipment
Experience in SerDes electrical compliance for industry standards such as PCIe and Ethernet is preferred
Experience in scripting test automation, demo GUIs, and customer-support scripts

Responsibilities

Involve in first-silicon bring-up of SerDes PHYs across PCIe and Ethernet protocols, and serve as the technical escalation point for customer SerDes issues across pre-silicon, bring-up, and production phases
Drive PCIe compliance, Ethernet IEEE compliance, and interop testing, and develop automated test scripts and regression suites for link stability, retry behavior, and stress conditions
Design, develop, and debug embedded firmware for high-speed SerDes systems spanning both electrical and optical domains, including configuration, monitoring, diagnostics, and adaptation hooks for electrical SerDes PHYs
Validate and characterize AMD’s SerDes PHY functionality and performance – electrical and/or optical – against design targets, product requirements, datasheets, and industry standards such as PCIe, IEEE, and OIF
Work closely with internal and external teams to troubleshoot issues, determine root cause, and feed lab learnings back to designers and architects for next-generation IP and design improvements
Develop test automation with advanced scripting and programming skills to improve test coverage, data analysis efficiency, and demo/customer-support tooling