Principal RTL Design Engineer
About The Position
SambaNova is seeking a Principal RTL Design Engineer to take ownership of the microarchitecture and RTL for their next-generation Reconfigurable Dataflow Unit (RDU), which is the silicon behind their AI acceleration systems. This is a senior individual contributor role where you will guide a block from microarchitecture specification through RTL, quality closure, and tape-out, managing power, performance, and area trade-offs. The role requires aggressive frequency targets, making datapath pipelining and strategic area allocation for timing crucial. The RTL design team is responsible for building the compute datapath, on-chip network, and memory subsystems within SambaNova's RDU AI accelerator. Their work encompasses microarchitecture through tape-out, including RTL implementation, PPA trade-offs, quality gates (lint, CDC, LEC), and timing closure with physical design.
Requirements
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 7+ years of industry experience in ASIC RTL design
- Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent
- High-frequency design experience, including datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets
- Deep foundation in computer architecture and digital logic design, including arbitration, flow control, clock domain crossing, and memory structures
- Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC
- Experience converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team
- Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows
- Demonstrated technical leadership without formal authority, including setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers
- Scripting in Python for design and flow automation
Nice To Haves
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
- Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem
- Industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
- AI and ML workload acceleration techniques, and dataflow or reconfigurable architectures
- Formal property checking applied to design intent
- Advanced TSMC nodes and multi-die or chiplet design
- Performance modeling and analysis to support architectural trade-offs
- Fluency with Claude or other AI tools applied to RTL design and flow development
Responsibilities
- Own the microarchitecture and RTL for a major block or subsystem of the RDU, from specification through tape-out, including the specs you write for complex blocks in compute, memory, or on-chip network subsystems
- Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle
- Own PPA for your area, hitting aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring
- Drive timing closure and design quality for your area: synthesis, STA, critical-path iteration, lint, CDC, LEC, and SystemVerilog Assertions capturing design intent
- Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures
- Work with architects and software teams to prototype and evaluate features that improve application-level performance
- Drive AI, automation, and new EDA tool methodologies into the design flow
- Set the technical bar in design reviews and mentor design engineers
Benefits
- Equity
- 95% premium coverage for employee medical insurance
- 77% premium coverage for dependents
- Health Savings Account (HSA) with employer contribution
- Dental insurance
- Vision insurance
- Short/Long term Disability insurance
- Basic Life insurance
- Voluntary Life insurance
- AD&D insurance
- Flexible Spending Account (FSA) options (Health Care, Limited Purpose, and Dependent Care)
- Well-being benefits
- Full subscription to Headspace
- Gympass+ membership with access to physical gyms
- One Medical membership
- Counseling services with an Employee Assistance Program
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What This Job Offers
Job Type
Full-time
Career Level
Principal
