Principal Physical Verification Engineer

Celero Communications • Irvine, CA

6d

About The Position

The Principal Physical Verification Engineer leads full-chip Physical Verification efforts, owning execution plans and schedules and driving quality, milestone accountability, and tapeout readiness. The role conducts full-chip and block-level Physical Verification checks and owns verification of the full chip.

The engineer runs and analyzes DRC/ERC/LUP/PERC results using ICV or Calibre verification tools and works with the internal analog team to support clean IP delivery. The role partners with analog, block, and chip-top owners to achieve a clean floorplan, provides early guidance on corner-case requirements, influences floorplan constraints, hierarchy, and implementation strategy, and participates in tapeout readiness reviews.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or a related field.
• 7+ years of experience with full-chip verifications.
• Hands-on experience with a Physical Verification tool such as ICV or Calibre.
• Ability to assemble a flow to support block- and chip-level Physical Verification.
• Strong expertise in floorplanning to avoid DRC/LVS issues.
• Understanding of advanced TSMC DRC rules.

Nice To Haves

• Experience with advanced technology nodes, including 7nm, 5nm, or 3nm.
• Automation skills using Tcl, Python, or shell scripting.

Responsibilities

• Lead full-chip Physical Verification efforts.
• Own execution plans and schedules for full-chip verification.
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full-chip and block-level Physical Verification checks.
• Own full-chip verification.
• Work with the internal analog team to ensure clean IP delivery.
• Run and analyze DRC/ERC/LUP/PERC results.
• Partner with analog, block, and chip-top owners to ensure a clean floorplan.
• Provide early guidance on corner-case requirements.
• Influence floorplan constraints, hierarchy, and implementation strategy.
• Participate in tapeout readiness reviews.
• Assemble a flow to support block- and chip-level Physical Verification.
• Provide guidance to the analog IP team to enable clean integration.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal