Principal Physical Verification Engineer

Celero Communications • San Jose, CA

5d

About The Position

The Principal Physical Verification Engineer leads full-chip physical verification, including planning and executing full-chip verification efforts and checks for both full-chip designs and blocks. The role owns verification execution plans and schedules, drives accountability for quality, milestones, and tapeout readiness, and runs and analyzes DRC, ERC, LUP, and PERC results. The engineer works with the internal analog team to support clean IP delivery and uses ICV or Calibre verification tools, with an understanding of advanced TSMC DRC rules.

The position collaborates with analog, block, and chip-top owners to support clean floorplans, provide early guidance on corner-case requirements, and influence floorplan constraints, hierarchy, and implementation strategy. It also participates in tapeout readiness reviews. The role requires assembling a physical verification flow for block- and chip-level work and providing guidance to the analog IP team to enable clean integration.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or a related field.
• At least 7 years of experience with full-chip verification.
• Hands-on experience with a physical verification tool such as ICV or Calibre.
• Ability to assemble a flow to support block- and chip-level physical verification.
• Strong expertise in floorplanning to avoid DRC/LVS issues.
• Understanding of advanced TSMC DRC rules.

Nice To Haves

• Experience with advanced technology nodes such as 7nm, 5nm, or 3nm.
• Automation skills using Tcl, Python, or shell scripting.

Responsibilities

• Lead full-chip physical verification efforts.
• Own execution plans and schedules for full-chip verification.
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct physical verification checks for full-chip designs and blocks.
• Own full-chip verification.
• Work with the internal analog team to ensure clean IP delivery.
• Run and analyze DRC, ERC, LUP, and PERC results.
• Partner with analog, block, and chip-top owners to ensure clean floorplans.
• Provide early guidance on corner-case requirements.
• Influence floorplan constraints, hierarchy, and implementation strategy.
• Participate in tapeout readiness reviews.
• Assemble a flow to support block- and chip-level physical verification.
• Provide guidance to the analog IP team to allow for clean integration.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal