Principal Physical Verification Engineer

Celero Communications • San Jose, CA

5d

About The Position

This role is for a Senior/Principal Full-Chip Physical Verification Engineer who will lead the full chip Physical Verification effort. The engineer will own execution plans, schedules, and drive accountability for quality, milestones, and tapeout readiness. Responsibilities include conducting full chip and blocks PV checks, owning full chip verification, and working with the internal analog team to ensure clean IP delivery. The role also involves running and analyzing DRC/ERC/LUP/PERC results, and understanding advanced TSMC DRC rules. Collaboration with analog, block, and chip top owners is crucial to ensure a clean floorplan, provide early guidance on corner case requirements, and influence floorplan constraints, hierarchy, and implementation strategy. Participation in tapeout readiness reviews is also expected.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or related field
• 7+ years of experience with full-chip verifications
• Proven hands-on experience with Physical Verification tool (ICV/Calibre)
• Able to assemble a flow to support block/chip level PV
• Strong expertise in Floorplanning to avoid DRC/LVS issues
• Provide guidance to analog IP team to allow for clean integration

Nice To Haves

• Experience in advanced technology nodes (7nm, 5nm, 3nm)
• Automation skills using Tcl, Python, or shell scripting

Responsibilities

• Lead full chip Physical Verification effort
• Own execution plans, schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness
• Conduct full chip and blocks PV checks
• Ownership of full chip verification
• Work with internal analog team to ensure clean IP delivery
• Responsible for running and analyzing DRC/ERC/LUP/PERC results
• Understanding advance TSMC DRC rules
• Partner with analog, block, chip top owners to ensure clean floorplan
• Provide early guidance on corner case requirements
• Influence floorplan constraints, hierarchy, and implementation strategy
• Participate in tapeout readiness reviews

Benefits

• Annual Base Salary Range: $150,000 - $250,000

What This Job Offers

• Job Type: Full-time
• Career Level: Senior