Principal Engineer - Verification

Microchip Technology Inc. • Chandler, AZ

1d • Onsite

About The Position

The dsPIC Business Unit is seeking a Principal Engineer – Verification to join our team in Chandler, Arizona. In this role, you will lead IP-level verification for dsPIC products using formal verification and UVM testbenches. You will work closely with cross-functional teams across the USA, India, and other global corporate teams to ensure high-quality verification results and timely project execution.

Microchip Technology Inc. is a global organization with a large, diverse team focused on designing technology that powers the world. We offer an atmosphere of trust, empowerment, respect, diversity, and communication, with opportunities for career growth and stability. Our culture supports employee development, values-based decision making, and a strong sense of community, recognized through numerous awards for diversity and workplace excellence. We are built by dedicated team players who challenge the status quo and are committed to empowering innovation.

Requirements

• Bachelor’s or master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• Minimum 10+ years of experience in functional verification.
• Strong expertise in SystemVerilog language, assertions, and UVM methodology.
• Proven experience building IP-level and SoC-level verification environments using UVM and/or formal verification Testbenches.
• Excellent understanding of digital design, RTL fundamentals, and ARM/RISC SoC architectures.
• Strong communication, teamwork, and problem-solving skills.
• Highly motivated, detail-oriented, and committed to delivering quality results on time.

Nice To Haves

• Demonstrated success in mentoring engineers and leading verification efforts across global teams.
• Experience driving methodology improvements and automation initiatives.

Responsibilities

• Architect, develop, and maintain UVM verification environments and Formal verification environments.
• Define verification plans and implement constrained-random UVM Testbench and/or Formal Testbench.
• Develop assertions and coverage in System Verilog language, analyze coverage metrics, and drive coverage closure.
• Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve defects.
• Collaborate with SoC development teams to integrate IP-level testbenches and tests into SoC-level verification environments.
• Collaborate with architects, designers, and applications teams to verify IP and product requirements and deliver quality results on schedule.
• Provide technical support and mentoring to verification engineers and drive projects to completion on schedule.
• Continuously improve verification methodologies by leveraging AI/ML automation to reduce the cycle time of verification.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal