Principal Memory Sub-System Validation Lead

Advanced Micro Devices, Inc•Santa Clara, CA

2d•Hybrid

About The Position

The Data Center Graphics and Accelerated Computing Validation Team is looking for a dynamic and energetic lead to join our growing post-silicon validation team. The Memory sub-system validation lead is responsible to drive and deliver pre- and post-silicon validation and characterization of on-die High-Bandwidth Memory (HBM) on AMD’s Datacenter GPU (Machine Instinct product). High Bandwidth Memory sub-system is at heart of complex technology that delivers industry leading Datacenter solutions for Machine Learning (ML), and High-Performance Computing (HPC). In this wide-ranging role, validation lead is the critical interface between DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams to ensure that advanced memory technologies are delivered from architecture to mass production to AMD’s quality and industry standards. The validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

Requirements

Experienced self-starter with the ability to execute complex test plans independently and collaborate with cross-function teams to debug and resolve issues.
Lead by example, and mentor junior engineers.
Hands-on with lab tools and comfortable working in a lab environment.
Extraordinary leadership skills and ability to inspire team members with an innate ability to see the bigger picture.
Excellent debugging skills. Proven ability to drive resolution of critical problems, while under pressure.
Ability to understand complex technical discussions, extract action plans, and to succinctly summarize complex details for executive reporting.
Ability to apply knowledge of other high-speed, high-performance memory technologies.
Able to comfortable working in lab environment.
Bachelors or Masters in Electrical or Computer Engineering.

Nice To Haves

Experience working with major DRAM memory vendors and validation of DRAM device is a plus.
Significant experience in DDR , LPDDR , HBM SoC validation, verification and debug of High-Bandwidth Memory sub-system.
Develop functional, electrical validation plans for memory features, align cross-functional teams on the support and validation plans.
Strong programming skills (C/C++, Python) and comfortable working on Linux or Windows platforms.
Experience in developing test cases for Machine Learning, High Performance Computing.
Able to work as a team and work efficiently in a dynamic environment and on multiple projects.

Responsibilities

Drive and deliver pre- and post-silicon validation and characterization of on-die High-Bandwidth Memory (HBM) on AMD’s Datacenter GPU (Machine Instinct product).
Act as a critical interface between DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams.
Ensure advanced memory technologies are delivered from architecture to mass production to AMD’s quality and industry standards.
Develop and execute test plans for HBM Functional and Electrical Validation (PVT Shmoo Characterization).
Debug skills to root cause post-production issues, customer returns.
Collaborate and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware and Software.
Drive debug in post silicon, root-cause problems and steer the team to the best corrective action to move forward.