Sr. Memory Validation Engineer

Ambarella•Headquarters, KY

1d•$152,000 - $179,000

About The Position

This role is for an engineer on the ASIC design team who will own the data and automation layer for the memory subsystem. The engineer will be responsible for building test infrastructure to catch instability early, turning lab and field data into insight, and feeding that information back into the design of next-generation memory controllers. The role involves both hands-on lab work during silicon bring-up and writing automation for debugging and validation.

Requirements

4+ years in memory validation, memory controller design, SoC validation, or a closely related area.
Hands-on experience with LPDDR5/5X and LPDDR6, and working familiarity with relevant JEDEC specifications.
Experience owning or contributing to memory training and calibration code, with C/firmware skills.
Strong Python (or equivalent) for test automation and data analysis.
Practical debug skills on real hardware: bench instrumentation, protocol analyzers, logic analyzers, boot and stability failure triage.
Comfort with data at scale to find signals in results.
Ability to work directly with customers and cross-functional teams under time pressure.

Nice To Haves

Silicon bring-up or post-silicon validation experience on a production program.
Signal integrity fundamentals: eye diagrams, jitter, and timing margin analysis on high-speed interfaces.
Experience with low-power state validation (self-refresh, power-down, DVFS-style transitions).
Statistical analysis, ML, or dashboarding experience applied to hardware validation data.
Firmware or driver-level exposure to the memory stack.

Responsibilities

Own the memory training and calibration code, developing, maintaining, and tuning routines for LPDDR5/5X and LPDDR6 reliability.
Collect and analyze memory subsystem data from lab testing, customer platforms, and internal validation systems.
Build automation for memory stability testing, performance characterization, speed binning, and regression analysis.
Debug customer issues alongside field teams and internal engineering groups, driving problems from report to closure.
Translate system behavior and failure analysis into insights to improve memory controller robustness and performance.
Propose architectural and design enhancements for next-generation memory controllers, supported by data and feedback.
Validate power-saving features against performance, reliability, and power targets.
Support silicon bring-up, qualification, and production readiness for memory subsystems.