Principal Engineer - Verification

Microchip•Chandler, AZ

22h•Onsite

About The Position

Microchip Technology Inc. is seeking a Principal Engineer – Verification to join the dsPIC Business Unit in Chandler, Arizona. This role involves leading IP-level verification for dsPIC products using formal verification and UVM testbenches. The engineer will collaborate with cross-functional teams globally to ensure high-quality verification results and timely project execution. Microchip offers a culture of trust, empowerment, respect, diversity, and communication, with opportunities for growth and stability within a multi-billion dollar global organization. The company is recognized for its employee development programs, values-based decision making, and strong community sense, supported by its Vision, Mission, and 11 Guiding Values (the Aggregate System). Microchip has a history of record revenue and over 30 years of quarterly profitability, driven by a team dedicated to empowering innovation.

Requirements

Bachelor’s or master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
Minimum 10+ years of experience in functional verification.
Strong expertise in SystemVerilog language, assertions, and UVM methodology.
Proven experience building IP-level and SoC-level verification environments using UVM and/or formal verification Testbenches.
Excellent understanding of digital design, RTL fundamentals, and ARM/RISC SoC architectures.
Strong communication, teamwork, and problem-solving skills.
Highly motivated, detail-oriented, and committed to delivering quality results on time.

Nice To Haves

Demonstrated success in mentoring engineers and leading verification efforts across global teams.
Experience driving methodology improvements and automation initiatives.

Responsibilities

Architect, develop, and maintain UVM verification environments and Formal verification environments.
Define verification plans and implement constrained-random UVM Testbench and/or Formal Testbench.
Develop assertions and coverage in System Verilog language, analyze coverage metrics, and drive coverage closure.
Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve defects.
Collaborate with SoC development teams to integrate IP-level testbenches and tests into SoC-level verification environments.
Collaborate with architects, designers, and applications teams to verify IP and product requirements and deliver quality results on schedule.
Provide technical support and mentoring to verification engineers and drive projects to completion on schedule.
Continuously improve verification methodologies by leveraging AI/ML automation to reduce the cycle time of verification.