Principal Engineer, SOC IP Systems & Lifecycle Management

Astera Labs • San Jose, CA

11d

About The Position

Astera Labs is seeking a Principal Engineer to lead the strategic development of their AI-powered IP Lifecycle Management and IP Quality Assurance Platform. This role involves architecting a scalable, user-friendly system to manage internal and external IPs, ensuring they are SOC-ready and preventing integration issues. The candidate will audit and qualify various IP types, ensuring they meet integration, timing, and manufacturability standards. The platform will scale to cover SOC QA and be a key element of tape-out sign-out requirements. The successful candidate will have expertise in running EDA tools, understanding results, identifying false positives, and resolving root causes of errors with vendors or internal teams.

Requirements

• Mastery of the full sign-off suite: PrimeTime, Fusion Compiler, Genus, Calibre, Innovus, IC Compiler, SpyGlass, Tessent, Liberate (/MX), PrimeSim.
• Cross-Tool Consistency expertise is a must.
• Expert in Tcl for tool manipulation and Python for building AI-wrapper layers.
• Familiarity with SystemVerilog.
• Deep understanding of FinFET/Gate-All-Around (GAA) properties, Electromigration (EM), and ESD rules.
• Deep knowledge of Liberty modeling and LEF/DEF physical formats.
• A "Detective" mindset with the ability to look past a "green" or “red” report to find false errors and rootcause real ones.
• Ability to work with design teams and IP vendors to solve issues in a timely manner.

Nice To Haves

• Experience with IP Management, Methodology and Quality Assurance Platform development.
• Experience with AI-powered IP Lifecycle Management.
• Experience with IP Quality Assurance Platform development.
• Experience with Hard/Soft Macros, PHYs, Memories and standard cells libraries auditing and qualification.

Responsibilities

• Architect and lead the integration of agentic AI workflows into the IPLM and IPQA platform to automate IP Management, root-cause analysis of false pass scenarios and self-heal real issues.
• Verify IP compliance with high-speed and high-bandwidth interface standards for heterogeneous integration (Chiplet Readiness).
• Architect automated audits for logical-to-physical consistency across RTL, Liberty, LEF, GDSII, and CDL views, focusing on pin-naming, bus-integrity, and functionality.
• Perform independent LVS, DRC, and Antenna signoffs using native runsets for 5nm/3nm and beyond nodes.
• Validate DFT requirements, including scan-chain integrity, MBIST handshakes, and fault-coverage transparency.
• Audit Power Domain (UPF/CPF) consistency and conduct deep-dive Liberty (.lib) audits to identify missing timing arcs or non-monotonic lookup tables.
• Audit IR-drop/EM (Electromigration) reports to ensure the IP won't cause localized power grid failures.
• Develop rigorous, automated Waiver Audit Protocol to ensure that provider-cleared violations do not violate Astera Labs' internal sign-off deck requirements.
• Track and check lessons learned from release to release, and generation to generation.
• Ensure releases are complete, patches are integrated, constraints are updated, and documentation reflects the updates including PPA impact.

Benefits

• Base salary range: $175,000.00 USD – $230,000.00 USD
• Salary determined based on location, experience, and pay of employees in similar positions.
• Encouragement for diverse ideas, backgrounds, and experiences.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: No Education Listed
• Number of Employees: 101-250 employees