Principal Design Engineer- Memory IP

Cadence Systems • San Jose, CA

4d

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Requirements

• Must have BS degree with 8+ years of applicable experience, MS degree with 6+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
• Essential that the individual demonstrates strong communication, verbal and written.
• Requires good communication skills in English.
• Familiar with JEDEC-DDR, and DFI protocols and have memory IP design experience

Nice To Haves

• At least six years experience working on digital IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.

Responsibilities

• Proficiency in logic design and micro-architecture
• Proficiency in Verilog/SystemVerilog and its simulation environment
• Good knowledge of IC design with high speed and low power

Benefits

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options

What This Job Offers

• Job Type: Full-time
• Career Level: Principal