Principal Engineer - Signal Integrity

Micron Technology • Boise, ID

1d

About The Position

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Within the larger SI R&D group, as a Principal Signal Integrity Engineer at Micron, you will be responsible for leading the development and analysis of high speed (HS or similar expertise) memory interfaces and power distribution networks (PDN). You will apply AI/ML and data-driven techniques to accelerate Signal Integrity / Power Integrity analysis, build optimization, and engineering decision-making. You will also apply automation, scripting, and AI-assisted engineering workflows to improve simulation efficiency and coverage. Representing the Signal Integrity R&D team in technical cross-functional collaborative groups, you will integrate with package build, silicon develop, system invent, product engineering, and marketing departments to ensure overall product performance. You will drive and develop SI/PI aspects of future standards (including but not limited to JEDEC, ONFI, and IBIS) through system and product electrical capability exploration, and support external customers as needed. You will formulate techniques and protocols for SI/PI analysis, and support and drive path-finding activities for IO and channel innovation to enable the next generation of memory technologies at higher speeds and densities.

Requirements

• PhD or MSEE, or equivalent experience, with at least 5 years of industry experience.
• Deep experience in Signal and Power Integrity, particularly in areas affecting I/O circuit signaling performance, PMICs, current workloads, PI performance & optimization.
• Required courses covering electromagnetic, transmission line and RF theory, and analog build or similar fields.
• Experience with E.M. field solvers (quasi-static and full wave), time and frequency domain simulation tools like Q3D, SIWAVE, HFSS, POWERSI, CLARITY, HSPICE, ADS, etc.
• Deep understanding of electromagnetic and transmission line theory, general I/O build, signal integrity, differential and single-ended interface technologies.
• Expertise in Printed Circuit Board (PCB) layout or electrical package development techniques.
• Experience in building and analyzing high-speed single-ended or differential buses.
• Familiarity with lab measurement equipment like Oscilloscopes, TDR, Vector Network Analyzer (VNA), etc.

Nice To Haves

• Familiarity with peak distortion analysis, statistical analysis (DOE), and equivalent tools (example: JMP) is beneficial.
• Memory industry experience is desired.
• Understanding of AI/ML is desired.
• Pro-active – Candidate is encouraged to recognize gaps and opportunities and address them with minimal supervision.
• Visionary – Candidate will be encouraged to think “outside-the-box” while providing innovative solutions within a set of practical constraints.
• Communicator – Candidate should be able to clearly express essential details of complex issues and related solutions in both written and verbal formats.

Responsibilities

• Leading the development and analysis of high speed (HS or similar expertise) memory interfaces and power distribution networks (PDN).
• Applying AI/ML and data-driven techniques to accelerate Signal Integrity / Power Integrity analysis, build optimization, and engineering decision-making.
• Applying automation, scripting, and AI-assisted engineering workflows to improve simulation efficiency and coverage.
• Representing the Signal Integrity R&D team in technical cross-functional collaborative groups, integrating with package build, silicon develop, system invent, product engineering, and marketing departments to ensure overall product performance.
• Driving and developing SI/PI aspects of future standards (including but not limited to JEDEC, ONFI, and IBIS) through system and product electrical capability exploration.
• Supporting external customers as needed.
• Formulating techniques and protocols for SI/PI analysis.
• Supporting and driving path-finding activities for IO and channel innovation to enable the next generation of memory technologies at higher speeds and densities.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Principal