Principal Engineer, Electrical Link Architecture

Ayar Labs • San Jose, CA

2d • Onsite

About The Position

Ayar Labs is developing co-packaged optics and silicon photonics solutions to address I/O bandwidth bottlenecks in modern AI computing. The Link Design and Architecture team is responsible for the performance and robustness of the company's optical links, from component models and architecture through link analysis, specifications, and yield.

The Principal Engineer, Electrical Link Architecture owns the electrical path of the optical link end to end, including analog front ends, equalization, clocking, and the models used to validate the design before silicon. The role determines how the link budget and equalization are divided between analog front ends and DSP, sets block specifications for the PHY and AMS teams, and correlates silicon results with models. It also assesses future link architectures as lane rates increase, considering power, system tradeoffs, and tapeout feasibility.

The position is based on-site in San Jose, California. The salary range is $224,000–$262,000. Ayar Labs is an Equal Opportunity Employer and provides reasonable accommodation when requested by qualified applicants or employees with disabilities, unless doing so would cause undue hardship.

Requirements

• Bachelor's degree in Electrical Engineering, Physics, or a related field.
• At least 8 years of experience in high-speed wireline or optical link design spanning both the analog front end and the equalization needed to close the link.
• Hands-on design or direct co-design experience with analog front-end blocks such as TIA, CTLE, VGA, sampler, TX driver, and clocking in a high-speed SerDes or optical transceiver.
• Deep understanding of how analog front-end bandwidth, noise, linearity, offset, and jitter affect the link, including the ability to reason from schematics and Spectre results rather than behavioral models.
• Strong command of equalization and clock recovery, including CTLE, FFE, DFE, MLSE, ADC-based receivers, adaptation, and CDR, and understanding of analog/DSP partitioning and how front-end non-idealities limit DSP recovery.
• Proficiency in Verilog-A and mixed-signal simulation; working fluency with Cadence Virtuoso, ADE, and Spectre.
• Experience with statistical circuit and link analysis, including corners, Monte Carlo, BER, and margin prediction.
• Strong Python skills for scientific computing.

Nice To Haves

• Master's or Ph.D. in Electrical Engineering, Physics, or a related field.
• Experience architecting a SerDes or optical PHY from concept through production silicon, including first-silicon debug.
• Direct experience with optical link electronics, including TIAs, high-swing modulator drivers, microring modulators and thermal control loops, and laser RIN and extinction-ratio budgeting.
• Experience with PAM4 and analog/DSP partitioning at 100 Gb/s per lane and above.
• Familiarity with chiplet/die-to-die interfaces such as UCIe, optical transceiver standards such as OIF CEI and IEEE 802.3, and shared link-simulation codebases.

Responsibilities

• Own the end-to-end electrical architecture and electrical link budget, covering the driver through modulator, photodetector through TIA, analog front end, equalization, and clock recovery.
• Determine how equalization and gain are partitioned between the analog front end and DSP, balancing power, area, and margin, and own the decision through tapeout.
• Translate link requirements into block-level electrical specifications, including bandwidth, noise, linearity, jitter, offset, and swing, for the AMS design team; sign off that designed blocks close the link at yield.
• Develop compact models of the analog front end and DSP chain at BER and link-margin fidelity, and Verilog-A models of the electrical/optical interface in collaboration with AMS and photonics teams.
• Lead silicon correlation for the electrical path with validation and SerDes characterization, changing the model or design when they disagree.
• Run statistical link analysis, including corners, Monte Carlo, and yield, in the team's in-house simulation stack; identify product specifications that cannot be met and present options.
• Explore next-generation electrical link architectures, including lane data rates, modulation formats, DSP-light versus ADC-based receivers, and new electrical/optical interfaces; provide tapeout recommendations and roadmap input.
• Represent electrical link architecture in cross-functional reviews, customer engagements, and foundry and EDA partner discussions.
• Mentor the team on analog front-end behavior.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal