Principal Engineer, Electrical Link Architecture
About The Position
Ayar Labs is developing co-packaged optics and silicon photonics solutions to address I/O bandwidth bottlenecks in modern AI compute architectures. The Link Design and Architecture team is responsible for the performance and robustness of the optical links, from component models through architecture, analysis, specifications, and yield. The Principal Engineer, Electrical Link Architecture owns the electrical path end to end, including analog front ends on both sides of the optics, equalization, clocking, and models used to evaluate the link before silicon exists. The role determines how the link budget is allocated across blocks and between the analog front end and DSP, sets block specifications for the PHY team, and reconciles silicon results against models. It also explores future link generations as lane rates increase, evaluates power and architecture tradeoffs, and turns system-level understanding of the analog front end and DSP into clear requirements for AMS and ASIC teams.
Requirements
- Bachelor’s degree in Electrical Engineering, Physics, or a related field.
- At least 8 years of experience in high-speed wireline or optical link design, spanning both analog front ends and link-closing equalization.
- Hands-on design or direct co-design experience with analog front-end blocks such as TIA, CTLE, VGA, sampler, TX driver, and clocking in a high-speed SerDes or optical transceiver.
- Deep understanding of how analog front-end bandwidth, noise, linearity, offset, and jitter affect the link, reasoned from schematics and Spectre results rather than behavioral models.
- Strong command of equalization and clock recovery, including CTLE, FFE, DFE, MLSE, ADC-based receivers, adaptation, and CDR; understanding of analog/DSP partitioning and how front-end non-idealities limit DSP recovery.
- Proficiency in Verilog-A and mixed-signal simulation.
- Working fluency with Cadence Virtuoso, ADE, and Spectre.
- Experience with statistical circuit and link analysis, including corners, Monte Carlo, and BER and margin prediction.
- Strong Python skills for scientific computing.
Nice To Haves
- Master’s or PhD in Electrical Engineering, Physics, or a related field.
- Experience architecting a SerDes or optical PHY from concept through production silicon, including first-silicon debug.
- Direct experience with optical link electronics, including TIAs, high-swing modulator drivers, microring modulators and thermal control loops, and laser RIN and extinction-ratio budgeting.
- Experience with PAM4 and analog/DSP partitioning at 100 Gb/s per lane and above.
- Familiarity with chiplet/die-to-die interfaces such as UCIe, optical transceiver standards such as OIF CEI and IEEE 802.3, and shared link-simulation codebases.
Responsibilities
- Own the end-to-end electrical architecture of the optical link, including driver through modulator, photodetector through TIA, analog front end, equalization, clock recovery, and the associated electrical link budget.
- Determine how equalization and gain are partitioned between the analog front end and DSP, balancing power, area, and margin, and own the decision through tapeout.
- Translate link requirements into block-level electrical specifications—including bandwidth, noise, linearity, jitter, offset, and swing—for the AMS design team, and sign off that designed blocks close the link at yield.
- Build compact models of the analog front end and DSP chain with BER and link-margin fidelity, and develop Verilog-A models of the electrical/optical interface in collaboration with AMS and photonics teams.
- Lead silicon correlation for the electrical path with validation and SerDes characterization, and drive changes to the model or design when results disagree.
- Run statistical link analysis, including corners, Monte Carlo, and yield, using the in-house simulation stack; identify product specifications that cannot be met and present options.
- Explore next-generation electrical link architectures, including data rate per lane, modulation format, DSP-light versus ADC-based receivers, and new electrical/optical interfaces; make tapeout recommendations and provide roadmap input.
- Represent electrical link architecture in cross-functional reviews, customer engagements, and foundry/EDA partner discussions.
- Mentor the team on analog front-end behavior.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
