Principal Engineer, Design For Test

Marvell Technology•Westborough, MA

About The Position

As a Digital IC Design Principal Engineer with Marvell, you’ll be a member of the Custom Silicon Engineering team. This team is a leader in large multi-die designs that are driving high compute performance and acceleration in many markets, including custom AI, 5G and 6G. The role will be challenging and will require an experienced DFT engineer that can work with existing DFT solutions while also creating new solutions to address industry first issues. The position will be responsible for architecting, leading and implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs. The execution involves Design-for-Test architecture definition, implementation of various DFT/DFX features, validation, IP-DFT, STA, pattern generation & post-silicon bring-up and debug for various designs/IPs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers to enable their development and ability to scale across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience.
Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
Direct DFT experience with at least 10 years in the custom chip design business.
Hands on working experience in various stages of DFT-Execution - SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bringup/Debug.
Thorough knowledge on various DFT/Test architecture solutions.
Involved in DFT-Architecture definition of at least one SoC Design.
Understanding of DFT Flows and Methodologies and Experience.
Prior experience in leading ASIC designs.

Responsibilities

Architecting, leading and implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs.
Design-for-Test architecture definition.
Implementation of various DFT/DFX features.
Validation, IP-DFT, STA, pattern generation & post-silicon bring-up and debug for various designs/IPs in Custom/Compute space.
Mentoring, guiding and driving a small team of engineers.
Definition and enhancement of DFT methodologies and tools.
Benchmarking DFT methodologies and tools.
Enabling new methodologies in the domain of DFT/Test.