Design For Test Engineer (Einfochips Inc)

Arrow Electronics • San Jose, CA

1d • $112,200 - $0 • Onsite

About The Position

eInfochips, an Arrow company, is seeking a Design For Test Engineer to implement DFT for 3nm and 5nm Networking chips. This role involves IP DFT work, RTL checks for scan-insertion compatibility, scan-insertion using Tessent, ATPG pattern generation, pattern simulation, mismatch debug, and MBIST and JTAG insertion and verification. The engineer will also be responsible for silicon debug and bring-up at both block and top levels, and scripting for DFT flow enhancement and automation.

Requirements

• 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing)
• MBIST Insertion and Verification
• Experience in IEEE 1149.1 JTAG Insertion and verification
• Scripting languages like Perl, Shell, TCL
• Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes
• Experience with Mentor Tessent
• B. Tech, M.Tech in Microelectronics/Electronics
• Excellent communicator

Responsibilities

• DFT implementation for 3nm and 5nm Networking chips
• IP DFT work
• RTL checks for scan-insertion compatibility using Synopsys Spyglass
• Scan-Insertion using Tessent
• ATPG pattern generation: Compressed and Uncompressed Mode
• Pattern Simulation: Without timing, With timing for different corners
• Mismatch debug using Verdi
• Scripting with Perl, Shell, TCL for DFT flow enhancement/automation
• Makefile enhancement using extended scripts and targets for flow enhancement
• MBIST Insertion and Verification
• Silicon debug and bring-up for block and top
• IEEE 1149.1 JTAG Insertion and verification
• Low power DFT

Benefits

• Medical, Dental, Vision Insurance
• 401k, With Matching Contributions
• Short-Term/Long-Term Disability Insurance
• Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
• Paid Time Off
• Tuition Reimbursement
• Growth Opportunities

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: Associate degree