Principal Engineer, DDR & NOC Architecture

Rivian•UNAVAILABLE, UNAVAILABLE

69d•Onsite

About The Position

Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations. We are looking for a Principal-level architect to lead the definition and evolution of next-generation Network-on-Chip (NOC) and DDR memory controller architecture for complex SoCs. This role owns architecture across the on-chip data fabric and external memory subsystem, with responsibility for performance, QoS, scalability, power, reliability, and system-level efficiency. The ideal candidate brings deep expertise in SoC interconnects, DDR subsystem architecture, performance modeling, and cross-functional technical leadership. They will work closely with system architecture, IP, design, verification, physical design, firmware, and product teams to translate product requirements into robust and production-ready architecture.

Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field
12+ years of experience in SoC or ASIC architecture with significant ownership of interconnect and memory subsystem design
Deep expertise in NOC architecture, including topology selection, arbitration, QoS, congestion handling, flow control, and performance optimization
Deep expertise in DDR memory controller architecture and system behavior under real workload conditions
Strong understanding of high-performance SoC design tradeoffs across performance, power, area, and scalability
Experience building architecture models and using data to drive technical decisions
Strong knowledge of traffic patterns from CPUs, GPUs, AI/ML accelerators, DMA engines, multimedia blocks, and other high-bandwidth clients
Proven track record of leading cross-functional technical efforts from concept through silicon
Strong written and verbal communication skills with the ability to influence across architecture, design, and product teams

Nice To Haves

Experience with LPDDR and/or DDR architectures used in high-performance and power-constrained systems
Experience with coherent and non-coherent interconnect fabrics
Familiarity with cache/memory hierarchy design and system-level performance tuning
Experience with safety, reliability, ECC, RAS, and functional robustness requirements
Experience in automotive, AI, edge compute, or other high-compute embedded platforms
Experience supporting post-silicon tuning and performance characterization

Responsibilities

Define end-to-end architecture for NOC and DDR memory controller subsystems in advanced SoCs
Drive architectural tradeoffs across bandwidth, latency, QoS, coherency, buffering, arbitration, congestion management, power, area, and reliability
Own memory subsystem strategy, including DDR controller architecture, scheduling policy, traffic shaping, address mapping, refresh impact, and system performance optimization
Define scalable NOC topology, routing, flow control, bandwidth allocation, and traffic isolation mechanisms for multi-client SoCs
Develop architecture specifications for interconnect and memory subsystems, including interfaces, performance targets, use models, and corner-case behavior
Lead performance modeling and analysis to evaluate workload behavior, bottlenecks, utilization, and worst-case traffic scenarios
Partner with system architects and domain leads to align subsystem architecture with product requirements and software use cases
Work with RTL, verification, and firmware teams to ensure clean architectural intent, measurable requirements, and efficient implementation
Review microarchitecture proposals and implementation choices to ensure consistency with system goals
Drive debug and root-cause analysis for architecture-related issues during pre-silicon and post-silicon phases
Mentor senior engineers and architects and raise the overall quality of architecture thinking across the organization