Principal Engineer ASIC or Sr Principal Engineer ASIC

Northrop Grumman•Manhattan Beach, CA

8d•$125,300 - $234,600•Onsite

About The Position

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Northrop Grumman Space Systems sector, Digital Space Technology group located in Manhattan Beach, California, is seeking a motivated candidate to join the Electronics and Payloads Directorate. The selected candidate will become a Principal Engineer ASIC or Sr. Principal Engineer ASIC. The qualified applicant will work on digital designs for cutting edge space applications.

Requirements

STEM Bachelor's degree with 5+ years of engineering experience; or a STEM Master's degree with 3+ years of experience; or a STEM PhD. degree with 1+ years of experience (for Principal level)
STEM Bachelor's degree with 8+ years of engineering experience; or a STEM Master's degree with 6+ years of experience; or a STEM PhD. degree with 4+ years of experience (for Sr. Principal level)
Experienced in RTL (VHDL or Verilog) design for space applications
Development of ASIC/FPGA architecture based on requirements
Must have the ability to obtain and maintain an active Government security clearance

Nice To Haves

Hands-on lab experience with testing of digital hardware is highly desired
Experience with RTL design using Xilinx Vivado or Microchip Libero
Experience in SystemVerilog/UVM methodology for verification
Experience in DSP for Digital Communications design
Experience in digital network design
Active DoD Clearance or equivalent

Responsibilities

Development of RTL Design for digital systems
Perform simulation and emulation (lab integration), synthesis, timing analysis, logic equivalency check, etc
Development of verification plans and verification test benches using VHDL or System Verilog
Performing trace requirements as well as performing review and audits on the simulation test procedures and test environment