Mid-End ASIC Engineer, Principal

Positron Corporation

7h • $190,000 - $280,000 • Remote

About The Position

We're looking for an exceptional Principal Mid-End ASIC Engineer to own synthesis, timing convergence, implementation readiness, and logical design quality across our AI accelerator roadmap. This is a deeply technical, hands-on engineering role responsible for transforming high-quality RTL into implementation-ready netlists while driving timing closure strategy, constraint development, physical-aware optimization, and close collaboration between RTL designers and backend implementation partners. You will serve as the technical bridge between architecture, RTL, verification, and physical implementation.

Requirements

• 12+ years of ASIC implementation experience, including multiple successful tapeouts.
• Expert-level proficiency in synthesis methodology and flow development.
• Deep expertise in timing closure across complex, multi-million-gate designs.
• Expert-level command of Cadence Genus and/or Synopsys Design Compiler.
• Strong SDC expertise, including constraint development and MMMC environments.
• A solid grasp of RTL design principles and implementation-friendly coding practices.
• Hands-on experience with advanced process nodes at 5nm and below.
• Strong Tcl and Python scripting ability for automation and flow development.
• Excellent debugging and root-cause analysis skills.

Nice To Haves

• Experience with AI accelerators, CPUs, or GPUs.
• Familiarity with LPDDR, PCIe, or SerDes interfaces.
• Exposure to chiplet-based architectures and multi-clock SoC designs.

Responsibilities

• Define and own synthesis methodology across current and future ASIC generations, including scalable flows for RTL synthesis, constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation.
• Establish signoff criteria and methodology for synthesis deliverables.
• Own hands-on synthesis using industry-leading EDA tools, including Cadence Genus and Synopsys Design Compiler (or equivalent).
• Develop and maintain SDC constraints, clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments.
• Drive continuous improvement of synthesis QoR.
• Own logical timing closure and drive optimization across frequency, area, power, congestion, and wireability.
• Perform root-cause analysis of timing bottlenecks and develop timing budgets across all chip partitions.
• Collaborate closely with architecture and RTL teams to eliminate timing risks before physical implementation.
• Partner closely with backend implementation engineers to drive physical-aware synthesis, retiming, register balancing, pipeline optimization, logic restructuring, and hierarchical timing budgeting.
• Ensure RTL is implementation-friendly from the outset.
• Partner closely with architecture, RTL, verification, physical design, DFT, IP providers, and backend design services to drive rapid issue resolution.
• Serve as Positron's synthesis technical lead with external implementation partners, reviewing QoR, timing, area reports, and constraint methodology, and defining acceptance criteria.
• Apply AI to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.

Benefits

• Fully company-paid medical, dental, and vision insurance for you and your dependents
• Company-paid life and disability coverage, with voluntary options to add more
• Supplemental hospital, critical illness, and accident coverage available
• Unlimited paid time off
• 13 paid company holidays
• Remote-first culture with a company-provided computer and home office setup
• Competitive salary and equity
• 401(k) with company matching, eligible from day one
• Visa Support (H-1B visa transfers for eligible candidates)

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: No Education Listed