ASIC Power Engineer, Principal

Positron Corporation

3h • $200,000 - $300,000 • Remote

About The Position

This role owns power architecture, estimation, optimization, and verification across Positron's AI accelerator roadmap. You will define power methodology from architectural modeling through silicon validation, ensuring industry-leading performance-per-watt while meeting aggressive power and thermal constraints. Success in this role looks like power estimates that consistently predict silicon behavior, sustained performance-per-watt leadership across Positron's product line, and a power architecture that is reused and extended across future generations of chips. Shape the power architecture foundation for a new generation of AI inference accelerators, with direct influence on Positron's performance-per-watt leadership. Work at the frontier of silicon and AI, on chips built specifically for the demands of large-scale LLM inference.

Requirements

• 12+ years of ASIC design experience.
• Deep expertise in low-power design techniques and methodologies.
• Hands-on experience with UPF/CPF power specification and verification flows.
• Expert-level proficiency with PrimePower and Joules or equivalent power analysis tools.
• Strong background working with advanced process nodes.
• A solid grasp of RTL design and its impact on chip power.
• Proven experience achieving aggressive power targets in production silicon.

Nice To Haves

• Experience with AI accelerator architectures.
• Familiarity with LPDDR and HBM memory interfaces.
• Working knowledge of PCIe.
• Experience with dynamic voltage and frequency scaling (DVFS).
• Exposure to thermal modeling.
• Hands-on experience with silicon power validation.

Responsibilities

• Own the overall chip power strategy, defining approaches for dynamic power, leakage, clock power, memory power, interconnect power, SerDes power, idle power, and peak power.
• Develop accurate power models across the full development lifecycle, from early architectural estimation through RTL and gate-level estimation.
• Perform vector-based and activity-driven power analysis to validate estimates against real workload behavior.
• Drive power optimization techniques including clock gating, operand isolation, power gating, voltage islands, and multi-Vt optimization.
• Apply memory, pipeline, toggle-reduction, and data-movement optimization techniques, including approaches tailored to AI workloads.
• Partner with the backend team on IR drop, electromigration (EM), power distribution, and power grid planning.
• Define power-on sequencing, power domains, reset sequencing, isolation, retention, and UPF/CPF specifications.
• Own power-aware simulation and UPF verification.
• Lead reset verification, low-power state validation, wakeup validation, and power sequencing verification.
• Partner closely with Architecture, RTL, Backend, Firmware, Thermal, Packaging, and System Engineering teams to align power decisions across the full chip development flow.
• Use AI-driven tools to improve power analysis, regression triage, power anomaly detection, activity clustering, and identification of optimization opportunities.

Benefits

• Fully company-paid medical, dental, and vision insurance for you and your dependents
• Company-paid life and disability coverage, with voluntary options to add more
• Supplemental hospital, critical illness, and accident coverage available
• Unlimited paid time off, we encourage everyone to truly unplug and recharge
• 13 paid company holidays
• Remote-first culture with a company-provided computer and home office setup
• Competitive salary and equity
• 401(k) with company matching, eligible from day one
• Visa Support (H-1B visa transfers for eligible candidates)

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: No Education Listed