Principal ASIC Design Engineer

Marvell Technology • Ottawa, ON

1d • CA$145,800 - CA$194,400

About The Position

As a Digital IC Design, Principal Engineer at Marvell, you will be part of the Central Engineering organization—the core hub of innovation that supports all business units across the company. If Marvell were a wheel, Central Engineering would be the central hub, delivering foundational IP leveraged by teams spanning Automotive, Storage, Security, and Networking. You will join a small, high-impact digital design team where your contributions directly influence multiple product lines and strategic initiatives. The team is composed of some of the industry’s strongest problem solvers, tackling complex silicon challenges that shape Marvell’s technology roadmap. In addition to supporting internal business units, this team collaborates with leading semiconductor companies and major global technology firms—organizations that are widely recognized and respected across the industry.

Requirements

• Bachelor’s degree in computer science, Electrical Engineering, or a related field with 10–20 years of relevant industry experience; or a Master’s/PhD in a related field with 8–20 years of experience.
• Strong foundation in ASIC design, verification, architecture, and front-end design methodologies.
• Solid understanding of ASIC back-end design, EDA tools, and associated design methodologies.
• Hands-on experience with SoC architecture, including processor cores, memory subsystems, and peripheral interfaces.
• Extensive experience with Verilog/SystemVerilog, including linting, synthesis, static timing analysis, clock and reset domain crossing (CDC/RDC), and formal equivalence checking between RTL and gate-level netlists.
• Proficiency in scripting and automation using languages such as Python or Perl.
• Demonstrated track record of delivering production-quality silicon on aggressive development timelines.

Nice To Haves

• Experience with high-speed protocol domains such as Ethernet, PCIe, and emerging standards (e.g., UALink) is a plus.
• Familiarity with applying AI/ML techniques to ASIC development is a plus.
• Experience designing, verifying, and testing high-speed datapath logic is a plus.
• Expertise working with large datapath FPGAs and advanced ASIC technology nodes is desirable.

Responsibilities

• Lead the development and deployment of design flows and methodologies that bridge front-end design and back-end physical implementation.
• Work cross-functionally with Architecture, RTL Design, Physical Design, Timing, and DFT teams to drive seamless integration throughout the SoC development lifecycle.
• Establish and drive EDA methodologies for front-end design, enabling early visibility into back-end physical design challenges while ensuring that design intent is accurately reflected through robust constraints and implementation strategies.
• Define and implement front-end methodologies for early-stage synthesis, static timing analysis, and clock/reset domain crossing (CDC/RDC).
• Develop and optimize flows that enable early detection of physical design and timing challenges, ensuring efficient handoff to back-end teams.
• Collaborate closely with physical design teams to provide high-quality constraints aligned with architectural and design intent.
• Drive the delivery of complex, high-performance, timing-critical designs across all phases of the SoC front-end design flow, including timing closure and power optimization.

Benefits

• Competitive compensation
• Great benefits
• Workstyle within an environment of shared collaboration, transparency, and inclusivity.
• Tools and resources they need to succeed in doing work that matters, and to grow and develop with us.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal