Senior ASIC Design Engineer

NVIDIASanta Clara, CA
$136,000 - $264,500Hybrid

About The Position

NVIDIA is looking for a Senior ASIC Design Engineer to join our System ASIC team. This role involves designing and implementing world-leading GPUs and SoCs. The System-ASIC team collaborates with the System Architecture team on product definitions, implements innovative flows to improve chip yield, addresses multiple sectors, and defines and implements Reset and Boot Architecture in complex GPU and Tegra chips. The team also handles the architecture, design, and synthesis of multiple System-level modules. NVIDIA is a company that constantly evolves, driven by opportunities that are challenging and impactful, aiming to amplify human creativity and intelligence.

Requirements

  • BS / MS in Microelectronics/ Electronic Engineering/ Computer Science and related (or equivalent experience).
  • 5+ years of ASIC design experience or SOC integration design / flow experience.
  • Fundamental digital design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
  • Strong coding skills in Perl, Python, C++, or other industry-standard scripting languages.
  • Basic understanding of verification methodology.
  • Excellent analytical and problem-solving skills and attention to detail.

Nice To Haves

  • Familiarity with ARM CPU and SoC system architecture, microprocessor, and microcontroller fundamentals (caches, buses, memory controllers, DMA, etc.).
  • Experience with reset controllers, boot, fuse controllers or UCIe protocol.
  • Hands-on experience in programming (C/C++) and scripting (Perl/Python).

Responsibilities

  • Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs.
  • Collaborate with architects, ASIC designers, and verification engineers to design sophisticated system-level modules such as Floorsweep, In-silicon measurement, Reset and Boot controllers.
  • Be responsible for the RTL design, logic synthesis, and timing analysis of several modules.
  • Integrate modules into the overall SOC design and work closely with other teams in the silicon bring-up process and ensure successful SOC level integration.
  • Identify and implement improvements in the current design flow and methodologies to improve efficiency and quality.

Benefits

  • equity
  • benefits
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