Principal Embedded Firmware Engineer — AI/HPC Networking Silicon

Cornelis Networks, Inc.•Boston, MA

4d•Remote

About The Position

Cornelis Networks is seeking a principal-level embedded engineer to architect firmware across its next-generation networking silicon for AI and HPC. The role focuses on management firmware that boots, secures, and controls on-chip compute engines used to accelerate collective communication, alongside broader embedded architecture across the platform. The engineer will own the infrastructure that makes these engines trustworthy and production-ready, rather than developing the collective algorithms themselves. The work combines hands-on architecture and firmware development with technical leadership and mentorship. It involves bare-metal firmware on a RISC-V management core, secure firmware loading, engine bring-up and supervision, and firmware validation using functional simulators and automated tests. The role is fully remote for employees residing in the United States and makes heavy use of AI tools across design, implementation, and testing.

Requirements

10+ years of embedded or firmware engineering experience, with a track record of software architecture and technical leadership.
Expertise in C; C++ is a plus.
Working knowledge of Python.
Deep experience with bare-metal firmware on constrained cores, including manually managed local memories and low-level bring-up.
Experience with secure boot or image authentication and hardware root-of-trust integration.
Experience programming hardware CSRs and co-designing register-level interfaces with silicon teams.
Demonstrated hands-on proficiency with AI-assisted engineering and the judgment to validate AI-generated work.

Nice To Haves

RISC-V firmware and toolchain experience.
Firmware orchestration for multi-core accelerator arrays.
Familiarity with hardware root-of-trust ecosystems such as Caliptra and with SHA-2 or signature verification.
Experience with code-generation toolchains such as SystemRDL, Kaitai, and CMake, and simulator-based co-verification.
Familiarity with emerging AI/HPC interconnect standards including Ultra Ethernet (UEC), UALink, and ESUN.
Background in HPC/AI networking, RDMA, or libfabric.

Responsibilities

Architect and implement bare-metal C firmware on a RISC-V management core to provision, boot, and supervise arrays of on-chip acceleration engines.
Own the secure firmware-loading pipeline, including fetching images from flash, coordinating hardware root-of-trust authentication, and distributing verified images to engine-local memories through on-chip fan-out or DMA hardware.
Build per-engine bring-up, reset sequencing, and health validation using control/status registers, including timeout and error handling and enforced security invariants.
Scale firmware distribution and bring-up across many engines and multiple dies, including runtime reboot and in-field firmware updates.
Define the hardware/software contract with ASIC and RTL teams using a datamodel-first workflow, such as SystemRDL, Kaitai, or YAML with generated code.
Validate firmware against functional simulators such as QEMU with automated unit and integration tests.
Set architecture standards, review designs and code, and mentor engineers.