Principal Embedded Firmware Engineer — AI/HPC Networking Silicon

Cornelis Networks, Inc.•Boston, MA

2d•Remote

About The Position

Cornelis Networks is seeking a principal-level embedded engineer to architect firmware for next-generation networking silicon used in AI and HPC datacenters. A central focus is management firmware that boots, secures, and controls on-chip compute engines that accelerate collective communication. The role owns the infrastructure that makes these engines trustworthy and production-ready, rather than development of the collective algorithms themselves. Work combines hands-on architecture and firmware development with technical leadership and mentorship, with extensive use of AI tools in design, implementation, and testing. The position is remote for employees residing in the United States. The engineer will develop bare-metal firmware on a RISC-V management core, build secure image-loading and engine bring-up flows, and scale provisioning and recovery across engines and dies. The role also involves defining hardware/software interfaces with ASIC and RTL teams, validating firmware using functional simulators and automated tests, establishing architecture standards, reviewing designs and code, and mentoring engineers.

Requirements

10+ years of embedded/firmware engineering experience, with a track record of software architecture and technical leadership.
Expertise in C; working knowledge of Python.
Deep experience with bare-metal firmware on constrained cores, including manually managed local memories and low-level bring-up.
Experience with secure boot or image authentication and hardware root-of-trust integration.
Experience programming hardware CSRs and co-designing register-level interfaces with silicon teams.
Demonstrated hands-on proficiency with AI-assisted engineering and judgment to validate AI-produced work.

Nice To Haves

C++ experience.
RISC-V firmware and toolchain experience.
Firmware orchestration for multi-core accelerator arrays.
Experience with hardware root-of-trust ecosystems such as Caliptra and SHA-2/signature verification.
Experience with code-generation toolchains such as SystemRDL, Kaitai, and CMake, and simulator-based co-verification.
Familiarity with emerging AI/HPC interconnect standards: Ultra Ethernet (UEC), UALink, and ESUN.
Background in HPC/AI networking, RDMA, or libfabric.

Responsibilities

Architect and implement bare-metal C firmware on a RISC-V management core to provision, boot, and supervise arrays of on-chip acceleration engines.
Own the secure firmware-loading pipeline, including fetching images from flash, coordinating hardware root-of-trust authentication, and distributing verified images to engine-local memories using on-chip fan-out/DMA hardware.
Build per-engine bring-up, reset sequencing, and health validation using control/status registers, with timeout and error handling and enforced security invariants.
Scale firmware distribution and bring-up across many engines and multiple dies, including runtime reboot and in-field firmware updates.
Define the hardware/software contract with ASIC and RTL teams using a datamodel-first workflow, such as SystemRDL or Kaitai and generated code.
Validate firmware against functional simulators such as QEMU with automated unit and integration tests.
Set architecture standards, review designs and code, and mentor engineers.